Entry/Exit Control To/From a Low Power State in a CPU with an Unprotected Pipeline

• US 20080068238A1
• Filed: 09/14/2007
• Published: 03/20/2008
• Est. Priority Date: 09/14/2006
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bell, David, Anderson, Timothy, Flores, Jose, Lell, Anthony, Nardini, Lewis
• Application Number:
  US11/855,585
• Publication Number:
  US 20080068238A1
• Time in Patent Office: Days
• US Class Current: 341/139
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic blocks and memory during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Claims

1. A power control apparatus comprising:

a programmable global power controller;

a plurality of local power controllers;

a plurality of logic and memory blocks to be controlled.

2. The power control apparatus of claim 1, wherein:

said programmable global power controller is operable to communicate with said local power controllers.

3. The power control apparatus of claim 2, wherein:

said programmable global power controller is operable to control the power consumption of said logic and memory blocks.

4. The power control apparatus of claim 2, wherein:

said programmable global power controller is operable to control the power consumption by controlling the clock frequencies of the said logic and memory blocks.

5. The power control apparatus of claim 1, wherein:

said programmable global power controller is operable to reduce the power consumption in response to detecting a lack of activity or access within said logic and memory blocks.

6. The power control apparatus of claim 5, wherein:

said programmable global power controller is operable to restore the power consumption to normal in response an external request.

7. A method of power control comprising the steps of:

generating an idle signal; and

reducing the power consumption of the logic element or memory block associated with the idle signal.

8. The method of claim 7 further comprising the steps of:

detecting an internal or external request; and

restoring the power state of the logic element or memory block associated with the request.

9. The method of claim 7 wherein:

said step of reducing the power consumption of said logic element or memory block includes adjusting the clock frequency of said logic element or memory block.