Entry/Exit Control To/From a Low Power State in a Complex Multi Level Memory System
First Claim
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1. A power control apparatus comprising:
- a programmable global power controller;
a plurality of local power controllers; and
a plurality of logic blocks to be controlled.
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Abstract
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
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Citations
9 Claims
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1. A power control apparatus comprising:
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a programmable global power controller; a plurality of local power controllers; and a plurality of logic blocks to be controlled. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of power control comprising the steps of:
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generating an idle signal; reducing the power consumption of the logic element associated with the idle signal. - View Dependent Claims (8, 9)
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Specification