Frame Rate Controller Method and System

• US 20080068404A1
• Filed: 09/19/2006
• Published: 03/20/2008
• Est. Priority Date: 09/19/2006
• Status: Abandoned Application

• Current Assignee: Tvia, Inc.
• Original Assignee: Tvia, Inc.
• Inventors: Ishii, Takatoshi
• Application Number:
  US11/533,321
• Publication Number:
  US 20080068404A1
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2320/0285 using tables for spatial correction of display data
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A frame rate controller method and system are provided. Aspects the exemplary embodiment include a data separator responsive to receiving display data comprising frames of digital pixel data for separating the display data into an integer part comprising upper bits of the display data, and a fraction part (Din_f) comprising lower bits of the display data; a high/low generator responsive to receiving the integer part for generating a data out high value and a data out low value, wherein the data out high value equals the integer part plus one and the low value equals the integer part; a multiplier responsive to receiving a frame counter value (Fc) and the Din_f for multiplying and outputing a first multiplication result of Din_f×(Fc+1), and a second multiplication result of Din_f×Fc; a pixel sequence LUT containing a pattern of sequence numbers, wherein the pixel sequence LUT outputs one of the sequence numbers based on horizontal pixel counter and vertical line counter values; a comparator for generating a code based on a comparison of the sequence number output from the pixel sequence LUT and the first and second values output from the multiplier, wherein the code comprises a first value and a second value; and a multiplexer for receiving the code and the data out high value and the data out low value from the high/low generator, and outputting the data out high value if the code equals the first value, and outputting the data out low value if the code equals the second value.

Claims

1. A frame rate controller comprising:

a data separator responsive to receiving display data comprising frames of digital pixel data for separating the display data into an integer part comprising upper bits of the display data, and a fraction part (Din_f) comprising lower bits of the display data;

a high/low generator responsive to receiving the integer part for generating a data out high value and a data out low value, wherein the data out high value equals the integer part plus one and the low value equals the integer part;

a multiplier responsive to receiving a frame counter value (Fc) and the Din_f for multiplying and outputing a first multiplication result of Din_f×

(Fc+1), and a second multiplication result of Din_f×

Fc;

a pixel sequence LUT containing a pattern of sequence numbers, wherein the pixel sequence LUT outputs one of the sequence numbers based on horizontal pixel counter and vertical line counter values;

a comparator for generating a code based on a comparison of the sequence number output from the pixel sequence LUT and the first and second values output from the multiplier, wherein the code comprises a first value and a second value; and

a multiplexer for receiving the code and the data out high value and the data out low value from the high/low generator, and outputting the data out high value if the code equals the first value, and outputting the data out low value if the code equals the second value.

2. The frame rate controller of claim 1 wherein the pixel sequence LUT comprises a 4×

4 matrix of storage locations, the pattern of sequence numbers being stored in the pixel sequence LUT by;

storing a first sequence number in a storage location identified by the starting point;

generating a set of candidate points to store a next sequence number by moving two positions straight from the storage location of the first sequence number, both vertically and horizontally, then one position to the side, both vertically and horizontally;

retaining only the candidate points falling within the boundary of the pattern;

randomly choosing one of the candidate points as the storage location for the next sequence number; and

repeating the generating, retaining and choosing steps until all sixteen sequence numbers are stored in the pattern.

3. The frame rate controller of claim 2 wherein all possible candidate points within the pattern are generated by moves from the last storage location within the pattern and from storage locations located in symmetrical positions of at least two 4×

4 patterns located at coordinates immediately adjacent to the pattern.

4. The frame rate controller of claim 2 wherein pixel sequence LUT has a 4-bit address, wherein two least significant bits of the horizontal pixel counter provide a lower 2-bits of the 4-bit address and a two least significant bits of the vertical pixel counter provide the higher 2-bits of the 4-bit address

5. The frame rate controller of claim 1 wherein the frame rate controller reduces a data width of the display data to match a data width of a source driver prior to display.

6. The frame rate controller of claim 1 wherein the data separator separates the display data into an integer part comprising upper bits of the display data, and a fraction part comprising lower bits of the display data.

7. The frame rate controller of claim 1 wherein the comparator compares the sequence number with ((Fc+1)×

Din_f) mod 16, and (Fc×

Din_f) mod 16 output of the multiplier to generate a value (0 or

     1) for the Code based on;

If (Fc) ×

(Din_f) = (Fc +

     1) ×

(Din_f) then Code =0 If (Fc) ×

(Din_f) <

(Fc +

     1) ×

(Din_f) then  

 

 

If (Fc) ×

(Din_f) <

= Seq_No <

(Fc +

     1) ×

(Din_f) then Code =1  

 

 

 

 

 

Else Code=0 If (Fc +

     1) ×

(Din_f) <

(Fc) ×

(Din_f) then  

 

 

If (Fc +

     1) ×

(Din_f) <

= Seq_No <

(Fc) ×

(Din_f) then Code = 0  

 

 

 

 

 

Else code =1

8. A method for generating a constant energy display, comprising:

receiving display data comprising frames of digital pixel data and separating the display data into an integer part comprising upper bits of the display data, and a fraction part (Din_f) comprising lower bits of the display data;

generating a data out high value and a data out low value, wherein the data out high value equals the integer part plus one and the low value equals the integer part;

receiving a frame counter value (Fc) and the Din_f and outputing a first multiplication result based on Din_f×

(Fc+1), and a second multiplication result based on Din_f×

Fc;

generating a sequence number based on a table lookup of horizontal pixel counter and vertical line counter values;

generating a code based on a comparison of the sequence number and the first and second values, wherein the code comprises a first value and a second value; and

outputting the data out high value if the code equals the first value, and outputting the data out low value if the code equals the second value.

9. The method of claim 8 wherein the pixel sequence LUT comprises a 4×

4 matrix of storage locations, the pattern of sequence numbers being stored in the pixel sequence LUT by;

storing a first sequence number in a storage location identified by the starting point;

generating a set of candidate points to store a next sequence number by moving two positions straight from the storage location of the first sequence number, both vertically and horizontally, then one position to the side, both vertically and horizontally;

retaining only the candidate points falling within the boundary of the pattern;

randomly choosing one of the candidate points as the storage location for the next sequence number; and

repeating the generating, retaining and choosing steps until all sixteen sequence numbers are stored in the pattern.

10. The method of claim 9 wherein all possible candidate points within the pattern are generated by moves from the last storage location within the pattern and from storage locations located in symmetrical positions of at least two 4×

4 patterns located at coordinates immediately adjacent to the pattern.

11. The method of claim 9 wherein pixel sequence LUT has a 4-bit address, wherein two least significant bits of the horizontal pixel counter provide a lower 2-bits of the 4-bit address and a two least significant bits of the vertical pixel counter provide the higher 2-bits of the 4-bit address

12. The method of claim 8 wherein a data width of the display data is reduced to match a data width of a source driver prior to display.

13. The method of claim 8 wherein the display data is separated into an integer part comprising upper bits of the display data, and a fraction part comprising lower bits of the display data.

14. The method of claim 8 wherein the comparing further comprises comparing the sequence number with ((Fc+1)×

Din_f) mod 16, and (Fc×

Din_f) mod 16 to generate a value (0 or

     1) for the Code based on;

If (Fc) ×

(Din_f) = (Fc +

     1) ×

(Din_f) then Code =0 If (Fc) ×

(Din_f) <

(Fc +

     1) ×

(Din_f) then  

 

 

If (Fc) ×

(Din_f) <

= Seq_No <

(Fc +

     1) ×

(Din_f) then Code =1  

 

 

 

 

 

Else Code=0 If (Fc +

     1) ×

(Din_f) <

(Fc) ×

(Din_f) then  

 

 

If (Fc +

     1) ×

(Din_f) <

= Seq_No <

(Fc) ×

(Din_f) then Code = 0  

 

 

 

 

 

Else code =1