Flash memory devices and programming methods for the same

• US 20080068883A1
• Filed: 01/10/2007
• Published: 03/20/2008
• Est. Priority Date: 09/15/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Young-Ho, Kang, Sang-Gu
• Granted Patent: US 7,539,063 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells into a provisional state according to the least significant bit, and programming the plurality of memory cells into the second through fourth states from the first and provisional states according to the most significant bit. Programming the plurality of memory cells into the second through fourth states includes simultaneously programming the plurality of memory cells at least partially into at least two states during one programming operation period.

Claims

1. A method of programming a flash memory device including a plurality of memory cells, each of the plurality of memory cells storing multi-bit data, the multi-bit data representing at least one of first through fourth states, and including a most significant bit and a least significant bit, the method comprising:

programming at least a first memory cell into a provisional state according to the least significant bit stored in the first memory cell; and

simultaneously programming a first portion of the plurality of memory cells into one of the second through fourth states from the first state, and a second portion of the plurality of memory cells into one of the second through fourth states from the provisional state according to the most significant bit stored in each memory cell.

2. The method of claim 1, wherein the programming of the first portion and the second portion is performed during one programming operation period.

3. The method as set forth in claim 1, wherein a verify-read voltage for programming the first memory cell into the provisional state is higher than a verify-read voltage corresponding to the second state, but lower than a verify-read voltage corresponding to the third state.

4. The method as set forth in claim 1, wherein the simultaneous programming further includes,

a first programming stage in which the memory cells are programmed into one of the second through fourth states from the first or provisional state, and

a second programming stage in which the memory cells are simultaneously programmed from the first or provisional state into states excluded from the first programming stage.

5. The method as set forth in claim 4, wherein the first programming stage programs memory cells from the provisional state to the fourth state.

6. The method as set forth in claim 4, wherein during the second programming stage, memory cells excluded from the first programming stage are simultaneously programmed from the first state into the second state and from the provisional state into the third state.

7. The method as set forth in claim 1, wherein the first, second, third and fourth states correspond to ‘

11’

, ‘

01’

, ‘

10’ and

‘

00’

, respectively, and the provisional state has an associated voltage level higher than a voltage level associated with the second state, but lower than a voltage level associated with the third state.

8. The method as set forth in claim 7, wherein the second programming stage includes,

verifying whether the memory cells have been programmed into the second and third states using two program loops including two verify-read operations.

9. The method as set forth in claim 2, wherein the one programming operation period is a program cycle for which bit data is written in an incremental step pulse programming (ISPP) mode.

10. A method of programming a flash memory device including a plurality of memory cells, each of the plurality of memory cells storing multi-bit data, the multi-bit data representing at least one of first through fourth states, and including a most significant bit and a least significant bit, the method comprising:

programming at least one of the plurality of memory cells into a provisional state according to the least significant bit stored in the at least one memory cell; and

programming a first portion of the plurality of memory cells into one of the second through fourth states from the first state, and programming a second portion of the plurality of memory cells into one of the second through fourth states from the provisional state in accordance with a selected one of a plurality of different programming modes.

11. The method as set forth in claim 10, wherein in a first programming mode, programming the first and second portion includes,

programming the first portion from the first state into the second, third or fourth state according to the most significant bit stored in each memory cell in the first portion of memory cells, and

programming the second portion from the provisional state into the second, third or fourth state according to the most significant bit stored in each memory cell in the second portion of memory cells, wherein

the programming of the first and second portions is performed simultaneously during one programming operation period.

12. The method as set forth in claim 11, wherein the first programming mode further includes,

a first programming stage for programming memory cells from the first or provisional state into one of the second through fourth states, and

a second programming stage for programming the memory cells from the first or provisional state into at least one state excluded from the first programming stage, the first and second programming stages being performed during the same programming operation period.

13. The method as set forth in claim 12, wherein during the first programming stage at least a portion of memory cells programmed into the provisional state are programmed into the fourth state .

14. The method as set forth in claim 12, wherein during the second programming stage, memory cells excluded from the first programming stage are simultaneously programmed from the first state into the second state and from the provisional state into the third state.

15. The method as set forth in claim 11, wherein the first, second, third and fourth states correspond to ‘

11’

, ‘

01’

, ‘

10’ and

‘

00’

, respectively, and the provisional state has an associated voltage level higher than a voltage level associated with the second state, but lower a voltage level associated with the third state.

16. The method as set forth in claim 12, wherein the programming operation period is a program cycle for which data is written in an incremental step pulse programming (ISPP) mode.

17. The method as set forth in claim 16, wherein the second programming stage includes,

verifying whether the memory cells have been programmed into the second and third states using two program loops including two verify-read operations.

18. The method as set forth in claim 11, wherein when a second program mode is selected, programming the first and second portions of memory cells includes,

programming the first portion of memory cells during a first programming operation period, and programming the second portion of memory cells during a second programming operation period.

19. The method as set forth in claim 18, wherein the second programming mode includes,

a first programming stage programming selected memory cells from the provisional state into the fourth state,

a second programming stage programming selected memory cells from the provisional state into the third state, and

a third programming stage programming selected memory cells from the first state into the second state.

20. The method as set forth in claim 19, wherein the first, second, third and fourth states correspond to ‘

11’

, ‘

01’

, ‘

10’ and

‘

00’

, respectively, and the provisional state has an associated voltage level higher than a voltage level associated with the second state, but lower a voltage level associated with the third state.

21. A flash memory device comprising:

a cell array including a plurality of memory cells, each memory cell storing multi-bit data, the multi-bit data representing at least one of first through fourth states and including at least a most significant bit and a least significant bit;

a voltage generator configured to generate and provide a program voltage and verify-read voltages to a word line of memory cells selected from the plurality of memory cells;

a page buffer coupled to bit lines of the plurality of memory cells, the page buffer being configured to write multi-bit data to the selected memory cells and conduct verify-read and read operations;

a program controller configured to regulate the page buffer and the voltage controller to program the most significant bits stored in the plurality of memory cells based on selected option information; and

a selector configured to select one of a plurality of different programming modes and generate the option information indicating the selected programming mode.

22. The flash memory device as set forth in claim 21, wherein when the option information corresponds to a first option, the program controller regulates the page buffer and the voltage generator to program the plurality of memory cells into two states during one programming cycle.

23. The flash memory device as set forth in claim 21, wherein the program controller regulates the page buffer and the voltage generator to program the plurality of memory cells from the first state or a provisional state into at least one of the second through fourth states in response to the most significant bit, the plurality of memory cells being programmed into at least two states during one programming cycle.

24. The flash memory device as set forth in claim 23, wherein the program controller performs a first programming stage to program the memory cells from the first or provisional state into at least one of the second through fourth stages and a second programming stage to program the memory cells from the first or provisional state into two states excluded from the first programming stage during the program cycle.

25. The flash memory device as set forth in claim 24, wherein the program controller programs the memory cells, which have been programmed into the provisional state during the first programming stage, into the fourth state.

26. The flash memory device as set forth in claim 25, wherein during the second programming stage, the program controller simultaneously programs the memory cells excluded from the first programming stage from the first state into the second state and from the provisional state into the third state.

27. The flash memory device as set forth in claim 26, wherein the first, second, third and fourth states correspond to ‘

11’

, ‘

01’

, ‘

10’ and

‘

00’

, respectively, and the provisional state has an associated voltage level higher than a voltage level associated with the second state, but lower a voltage level associated with the third state.

28. The flash memory device as set forth in claim 26, wherein the program controller regulates the voltage generator and the page buffer to verify whether the memory cells have been programmed into the second and third states in one program loop during the second programming stage by performing two verify-read operations.

29. The flash memory device as set forth in claim 21, wherein when the option information corresponds to a second option, the program controller regulates the page buffer and the voltage generator to program the plurality of memory cells into one state during one programming cycle.

30. The flash memory device as set forth in claim 29, wherein the program controller programs selected memory cells from a provisional state into the third or the fourth state and from the first state into the second state.

31. The flash memory device as set forth in claim 30, wherein the first, second, third and fourth states correspond to ‘

11’

, ‘

01’

, ‘

10’ and

‘

00’

, respectively, and the provisional state has an associated voltage level higher than a voltage level associated with the second state, but lower a voltage level associated with the third state.

32. The flash memory device as set forth in claim 21, wherein the page buffer includes,

a first latch configured to store data corresponding to a programmed result associated with the least significant bit, and

a second latch configured to store the most significant bit to be programmed.