System and method for providing programmable delay read data strobe gating with voltage and temperature compensation

• US 20080068904A1
• Filed: 09/19/2006
• Published: 03/20/2008
• Est. Priority Date: 09/19/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Hughes, Thomas
• Granted Patent: US 7,405,984 B2
• Time in Patent Office: Days
• US Class Current: 365/193
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The present invention is a method for providing programmable delay read data strobe gating with voltage and temperature compensation. The method includes receiving a training request. The method further includes calibrating programmable delay lines for operating frequency and voltage and temperature variation. The method further includes locking to a first feedback signal. The method further includes storing a first feedback lock setting corresponding to the locked-to first feedback signal. The method further includes granting the training request. Additionally, when training is completed, the method further includes recalibrating the programmable delay lines for operating frequency and voltage and temperature variation.

Claims

1. A method for providing programmable delay read data strobe gating with voltage and temperature compensation, comprising:

receiving a training request;

calibrating programmable delay lines for operating frequency and voltage and temperature variation;

locking to a first feedback signal;

storing a first feedback lock setting corresponding to the locked-to first feedback signal;

granting the training request; and

when training is completed, recalibrating the programmable delay lines for operating frequency and voltage and temperature variation.

2. A method as claimed in claim 1, further comprising:

when training is completed, locking to a second feedback signal.

3. A method as claimed in claim 2, further comprising:

storing a second feedback lock setting corresponding to the locked-to second feedback signal without overwriting the previously stored first feedback lock setting.

4. A method as claimed in claim 3, further comprising:

comparing the second feedback lock setting to the first feedback lock setting.

5. A method as claimed in claim 4, further comprising:

adjusting delay settings of the programmable delay lines based upon a difference between the first feedback lock setting and the second feedback lock setting, the adjusted delay settings being compensated for voltage and temperature variation.

6. A method as claimed in claim 1, wherein the step of calibrating programmable delay lines for operating frequency and voltage and temperature variation includes:

when the programmable delay lines are offline, passing a first pulse through the upper delay line;

passing a second pulse through the lower delay line, the lower delay line delay settings allowing the second pulse to arrive at an output of the lower delay line one ¼

cycle after the first pulse returns to zero;

transmitting the first pulse and the second pulse to an AND logic gate; and

adjusting a variable fine delay setting of the upper delay line until a coinciding pulse is detected at an output of the AND logic gate.

7. A method as claimed in claim 1, wherein the step of locking to the first feedback signal includes:

passing a first pulse through the upper delay line;

transmitting the first pulse to an AND logic gate;

transmitting the first feedback signal to the AND logic gate;

when the first pulse is zero and before the first feedback signal rises, adjusting settings of the upper delay line until a converging pulse is detected at the output of the AND logic gate; and

when the converging pulse is detected at the output of the AND logic gate, locking the first feedback signal to a reference clock.

8. A method as claimed in claim 6, wherein the coinciding pulse is generated when the first pulse and the second pulse coincide at the AND logic gate.

9. A method as claimed in claim 7, wherein the converging pulse is generated when the first pulse and the first feedback signal converge at the AND logic gate.

10. A method as claimed in claim 6, further comprising:

mapping the programmable delay lines to an eight element delay line configuration.

11. A computer-readable medium having computer-executable instructions for performing a method for providing programmable delay read data strobe gating with voltage and temperature compensation, said method comprising:

receiving a training request;

calibrating programmable delay lines for operating frequency and voltage and temperature variation;

locking to a first feedback signal;

storing a first feedback lock setting corresponding to the locked-to first feedback signal;

granting the training request; and

when training is completed, recalibrating the programmable delay lines for operating frequency and voltage and temperature variation.

12. A computer-readable medium as claimed in claim 11, said method further comprising:

when training is completed, locking to a second feedback signal.

13. A computer-readable medium as claimed in claim 12, said method further comprising:

storing a second feedback lock setting corresponding to the locked-to second feedback signal without overwriting the previously stored first feedback lock setting.

14. A computer-readable medium as claimed in claim 13, said method further comprising:

comparing the second feedback lock setting to the first feedback lock setting.

15. A computer-readable medium as claimed in claim 14, said method further comprising:

adjusting delay settings of the programmable delay lines based upon a difference between the first feedback lock setting and the second feedback lock setting, the adjusted delay settings being compensated for voltage and temperature variation.

16. A computer-readable medium as claimed in claim 11, wherein the step of calibrating programmable delay lines for operating frequency and voltage and temperature variation includes:

when the programmable delay lines are offline, passing a first pulse through the upper delay line;

passing a second pulse through the lower delay line, the lower delay line delay settings allowing the second pulse to arrive at an output of the lower delay line one ¼

cycle after the first pulse returns to zero;

transmitting the first pulse and the second pulse to an AND logic gate;

adjusting a variable fine delay setting of the upper delay line until a coinciding pulse is detected at an output of the AND logic gate; and

mapping the programmable delay lines to an eight element delay line configuration.

17. A computer-readable medium as claimed in claim 11, wherein the step of locking to the first feedback signal includes:

passing a first pulse through the upper delay line;

transmitting the first pulse to an AND logic gate;

transmitting the first feedback signal to the AND logic gate;

when the first pulse is zero and before the first feedback signal rises, adjusting settings of the upper delay line until a converging pulse is detected at the output of the AND logic gate; and

when the converging pulse is detected at the output of the AND logic gate, locking the first feedback signal to a reference clock.

18. A computer-readable medium as claimed in claim 16, wherein the coinciding pulse is generated when the first pulse and the second pulse coincide at the AND logic gate.

19. A computer-readable medium as claimed in claim 17, wherein the converging pulse is generated when the first pulse and the first feedback signal converge at the AND logic gate.

20. A system for providing programmable delay read data strobe gating with voltage and temperature compensation, comprising:

means for receiving a training request;

means for calibrating programmable delay lines for operating frequency and voltage and temperature variation;

means for locking to a first feedback signal;

means for storing a first feedback lock setting corresponding to the locked to first feedback signal;

means for granting the training request; and

when training is completed, means for recalibrating the programmable delay lines for operating frequency and voltage and temperature variation.