MEANS AND APPARATUS FOR A SCALABLE CONGESTION FREE SWITCHING SYSTEM WITH INTELLIGENT CONTROL

• US 20080069125A1
• Filed: 11/29/2007
• Published: 03/20/2008
• Est. Priority Date: 07/31/2001
• Status: Abandoned Application

• Current Assignee: Interactic Holdings LLC
• Original Assignee: Interactic Holdings LLC
• Inventors: Hesse, John, Reed, Coke
• Application Number:
  US11/947,209
• Publication Number:
  US 20080069125A1
• Time in Patent Office: Days
• US Class Current: 370/410
• CPC Class Codes: H04L 47/12 Avoiding congestion; Recovering from congestion
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling

Abstract

This invention is directed to a parallel, control-information generation, distribution and processing system. This scalable, pipelined control and switching system efficiently and fairly manages a plurality of incoming data streams, and applies class and quality of service requirements. The present invention also uses scalable MLML switch fabrics to control a data packet switch, including a request-processing switch used to control the data-packet switch. Also included is a request processor for each output port, which manages and approves all data flow to that output port, and an answer switch which transmits answer packets from request processors back to requesting input ports.

Claims

1. An internet protocol switching system comprising a plurality of input ports connected by a data switch S to a plurality of output ports, having an input port A as one of the plurality of input ports and an output port X as one of the plurality of output ports, and

a message packet MA at input port A, wherein a decision to inject message packet MA into S is based at least in part on logic associated with output port X.

2. An internet protocol switching system in accordance with claim 1, further including an input port B and a message packet MB at input port B wherein the logic at output port X bases in part the decision to inject message packet MA into data switch S on information about message MB.

3. An internet protocol switching system in accordance with claim 2, wherein message packets MA and MB are targeted for output port X.

4. An internet protocol switching system in accordance with claim 2, wherein the timing of the injection of MA into data switch S depends at least in part on the arrival of one or more message packets at input port B.

7. An internet protocol switching system in accordance with claim 1 wherein the message packet MA is sub-divided into segments and a decision to inject a plurality of segments of MA into data switch S depends at least in part on logic associated with output port X.

8. An internet protocol switching system in accordance with claim 1 wherein the message packet MA and a message packet MB from input port B are scheduled to enter data switch S in such a way that message packet MA and message packet MB enter output port X concurrently.

9. An internet protocol switching system in accordance with claim 4, wherein the logic L associated with output port X sets a time for input port A to begin sending message packet MA into data switch S.

5. A method for sending a message packet MA through an interconnect structure, said interconnect structure having at least two input ports A and B, the message packet MA arriving at input port A, the method comprising the steps of:

monitoring the arrival of individual message packets at input port B; and

basing the possible scheduling of the injection of all or part of message packet MA into the interconnect structure, at least in part on the monitoring of individual message packets arriving at input port B.

10. A method in accordance with claim 5 wherein the monitoring of arriving message packets targeted for output port X is done by logic at X.

6. A method for sending a message MA through an interconnect structure, said interconnect structure having an input port A and a plurality of output ports including an output port X, and all or part of message MA arriving at input port A, the method comprising the steps of:

monitoring logic associated with output port X; and

basing a decision to inject message MA into the interconnect structure, at least in part on information concerning a message MB targeted for X and entering the interconnect structure at an input other than A