VARIABLE TIME DIVISION MULTIPLEX TRANSMISSION SYSTEM

• US 20080069151A1
• Filed: 09/19/2007
• Published: 03/20/2008
• Est. Priority Date: 12/28/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kondoh, Hitoshi, Satoh, Masahito, Nakao, Shigetoshi
• Granted Patent: US 7,830,906 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: G06F 13/372 using a time-dependent priority, e.g. individually loaded time counters or time slot
• CPC Class Codes: H04J 3/1682 Allocation of channels according to the instantaneous demands of the users, e.g. concentrated multiplexers, statistical multiplexers
• CPC Class Codes: H04L 12/417 with deterministic access, e.g. token passing
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5675 Timeslot assignment, e.g. TDMA
• CPC Class Codes: H04L 47/10 Flow control; Congestion control

Abstract

A time division multiplex transmission system transmits information on multiple channels by using a transmission path with variable time division multiplexing. The variable time division multiplex transmission system of this invention is equipped with multiple channel devices 30 and a single transmission path 5 connected to these multiple channel devices. The multiple channel devices 30 transmit or receive data over the transmission path. Additionally, the system is equipped with a circuit that determines consecutive time slots for using the transmission path, and each of the channel devices transmits or receives data using consecutive time slots. Data can be transmitted in two or more different transmission bands, and the different transmission bands are realized by making the number of time slots used for a communication frame different.

Claims

1-23. -23. (canceled)

24. A system for variable time division multiplex transmission between a master device and a plurality of slave devices included in a slave device group, the system comprising:

said master device including;

a synchronous clock signal terminal connected to a first clock line to which a synchronous clock signal is supplied;

a frame synchronous signal terminal connected to a second clock line to which a frame synchronous signal is supplied;

a data output terminal connected to a first data line to which a command and data are supplied; and

a data input terminal connected to a second data line to which a command and data are supplied;

and each of said slave devices including;

a synchronous clock signal input terminal connected to said first clock line;

a frame synchronous signal input terminal connected to said second clock line;

a data input terminal connected to said first data line;

a data output terminal connected to said second data line;

a daisy-chain input terminal;

a daisy-chain output terminal; and

a device identifier setting circuit;

the device identifier setting circuit comprising a device identifier holding circuit that holds a device identifier that shows a location of the slave device in the slave device group;

wherein a predetermined logic signal is applied to the daisy-chain input terminal of a first-stage slave device of said plurality of slave devices;

the daisy-chain output terminal of the first-stage slave device is connected to the daisy-chain input terminal of a next-stage slave device; and

said plurality of slave devices are connected in a cascade connection with the daisy-chain output terminals and the daisy-chain input terminals; and

wherein, when said master device supplies a device identifier setting command to said first data line in synchronization with said frame synchronous signal, the first-stage slave device sets a predetermined device identifier to said device identifier holding circuit and outputs a device identifier setting token from said daisy-chain output terminal, in response to said frame synchronous signal, said device identifier setting command and the logic signal of said daisy-chain input terminal; and

the next-stage slave device sets a predetermined device identifier to said device identifier holding circuit and outputs a device identifier setting token from said daisy-chain output terminal, in response to said frame synchronous signal, said device identifier setting command and said device identifier setting token; and

a predetermined device identifier is set respectively to said device identifier holding circuit of each of said slave devices.

31. The system of claim 24, wherein the signals supplied to said first data line and said second data line have a plurality of time slots in one frame that is defined by said frame synchronous signal, and said master device and said slave device perform data transmission and reception by using a predetermined time slot.

32. The system of claims 24, wherein said one frame is defined by pulses of said frame synchronous signal that is equivalent to time width of a plurality of periods of said synchronous clock signal.

33. The system of claim 24, wherein the pulse of said frame synchronous signal has a time width of two periods of said synchronous clock signal.

34. The system of claim 24, wherein each of said slave devices has a time slot allocation circuit that comprises:

a time slot number holding circuit that holds the number of time slot that can be used by the slave device in a plurality of time slots in one frame;

a time slot location indicating circuit that is connected to said synchronous clock signal input terminal and said frame synchronous signal input terminal, and outputs a time slot signal that shows one time slot in accordance with said synchronous clock signal and said frame synchronous signal; and

a time slot allocation token supply circuit connected to said synchronous clock signal input terminal, said frame synchronous signal input terminal, said daisy-chain input terminal, and said daisy-chain output terminal, and generates a time slot allocation token;

wherein, when said master device supplies data for said slave device onto said first data line in synchronization with said synchronous clock signal and said frame synchronous signal, the first-stage slave device generates a slot allocation token for the next-stage slave device in accordance with said time slot signal and said time slot number, and outputs the slot allocation token from said daisy-chain output terminal; and

the next-stage slave device generates a slot allocation token for a next-stage slave device, in accordance with said time slot signal, said time slot number, and said slot allocation token that is supplied to said daisy-chain input terminal, and outputs the slot allocation token from said daisy-chain output terminal.

35. The system of claim 24, wherein said master device and said slave device are semiconductor integrated circuits.