Digital adaptation circuitry and methods for programmable logic devices

• US 20080069276A1
• Filed: 09/14/2006
• Published: 03/20/2008
• Est. Priority Date: 09/14/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lai, Tin H., Tran, Thungoc M., Wong, Wilson, Shumarayev, Sergey, Hoang, Tim Tri, Chan, Doris Po Ching, Maangat, Simardeep
• Granted Patent: US 7,920,621 B2
• Time in Patent Office: Days
• US Class Current: 375/350
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Claims

1. A method of controlling equalization of an incoming data signal comprising:

detecting two successive differently valued bits in the data signal;

determining whether a transition in the incoming data signal between the two bits is relatively late or relatively early; and

increasing the equalization of the incoming data signal if the transition is relatively late.

2. The method defined in claim 1 further comprising:

decreasing the equalization of the incoming data signal if the transition is relatively early.

3. The method defined in claim 1 wherein the performing is performed only when a predetermined pattern of successive bit values precedes the transition.

4. The method defined in claim 3 wherein the predetermined pattern includes a plurality of similarly valued bits.

5. The method defined in claim 1 wherein the detecting and determining are performed repeatedly, and wherein the increasing is performed only when, in a plurality of performances of the detecting and determining, the transitions are more often relatively late than relatively early.

6. The method defined in claim 5 wherein, if, in the plurality of performances of the detecting and determining, the transitions are more often relatively early than relatively late, then decreasing the equalization of the incoming data signal.

7. The method defined in claim 1 wherein the determining comprises:

sampling the data signal when the transition should be occurring to produce a transition sample; and

comparing the transition sample to a reference value.

8. The method defined in claim 7 further comprising:

deriving the reference value from one of the two successive differently valued bits.

9. A method of controlling equalization of an incoming data signal comprising:

sampling the incoming data signal at times when data values in that signal should be stable, to produce data samples;

sampling the incoming data signal at times when that signal should be in transition between successive data values that are different from one another, to produce transition samples;

comparing a transition sample taken between two successive differently valued data samples to a reference value; and

controlling the equalization based on a result of the comparing.

10. The method defined in claim 9 wherein the reference value is one of the two successive differently valued data samples.

11. The method defined in claim 10 wherein the controlling comprises:

increasing the equalization if the comparing shows that the transition sample has a value that is the same as the value of the first of the two successive data samples.

12. The method defined in claim 10 wherein the controlling comprises:

decreasing the equalization if the comparing shows that the transition sample has a value that is the same as the value of the second of the two successive data samples.

13. The method defined in claim 9 further comprising:

examining the incoming data signal for a pattern of successive data samples that includes a plurality of similarly valued data samples followed by a differently valued data sample; and

performing the comparing only in response to detection of the pattern.

14. The method defined in claim 13 wherein the comparing is performed using the transition sample between the differently valued data sample and the plurality of similarly valued data samples.

15. The method defined in claim 9 wherein the controlling comprises:

integrating the result of the comparing over a plurality of successive performances of the comparing, and controlling the equalization based on a result of the integrating.

16. Circuitry for equalizing an incoming data signal comprising:

first sampling circuitry for sampling the incoming data signal at times when data values in that signal should be stable, to produce data samples;

second sampling circuitry for sampling the incoming data signal at times when that signal should be in transition between successive data values that are different from one another, to produce transition samples;

comparison circuitry for comparing a transition sample taken between two successive differently valued data samples to a reference value; and

equalization control circuitry for controlling equalization of the incoming data signal based on an output of the comparison circuitry.

17. The circuitry defined in claim 16 wherein the reference value is one of the two successive differently valued data samples.

18. The circuitry defined in claim 17 wherein the equalization control circuitry increases the equalization if the transition sample has a value that is the same as the value of the first of the two successive data samples.

19. The circuitry defined in claim 17 wherein the equalization control circuitry decreases the equalization if the transition sample has a value that is the same as the value of the second of the two successive data samples.

20. The circuitry defined in claim 16 wherein the equalization control circuitry comprises:

circuitry for integrating the output over time and for using a result of the integrating to determine whether to increase or decrease the equalization.

21. The circuitry defined in claim 16 further comprising:

pattern detection circuitry for detecting occurrence of a predetermined pattern of values in a plurality of successive ones of the data samples and for enabling the equalization control circuitry when that pattern is detected.

22. The circuitry defined in claim 21 wherein the predetermined pattern comprises multiple similarly valued data samples followed by a differently valued data sample.