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METHODS AND ARRANGEMENTS FOR LINK POWER REDUCTION

  • US 20080069279A1
  • Filed: 11/15/2007
  • Published: 03/20/2008
  • Est. Priority Date: 12/22/2003
  • Status: Active Grant
First Claim
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1. An apparatus for reducing power consumption by a clock and data recovery loop circuit, comprising:

  • a flywheel to monitor adjustments made in a phase of a sampling clock by a phase controller, the sampling clock being generated to sample bit values from a data signal, and to modify the adjustments in the phase of the sampling clock to track a phase of the data signal; and

    a loop latency controller to monitor the modifications of the adjustments to the phase of the sampling clock, to determine the existence of spread spectrum clocking based upon a pattern of the modifications, and, in response, to adapt a stage of the clock and data recovery loop circuit to operate with less power consumption.

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