Efficient pitch multiplication process

• US 20080070165A1
• Filed: 09/14/2006
• Published: 03/20/2008
• Est. Priority Date: 09/14/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fischer, Mark, Manning, H. Montgomery, Russell, Stephen
• Granted Patent: US 7,666,578 B2
• Time in Patent Office: Days
• US Class Current: 430/314
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Abstract

Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.

Claims

1. A method for integrated circuit fabrication, comprising:

patterning a first photoresist layer to form a photoresist pattern over a substrate;

transferring the photoresist pattern to a hardmask layer underlying the photoresist layer and a temporary layer underlying the hardmask layer;

forming spacers on sidewalls of elements in the patterned hardmask and temporary layers;

depositing a second photoresist layer over the spacers and the patterned hardmask and temporary layers;

patterning the second photoresist layer to expose some parts of the patterned hardmask and temporary layers and to expose some of the spacers while leaving photoresist directly over other parts of the patterned hardmask and temporary layers and over others of the spacers;

subsequently preferentially removing the exposed parts of the patterned hardmask and temporary layers; and

preferentially removing the second photoresist layer.

2. The method of claim 1, further comprising subsequently transferring a pattern defined by the spacers and the remaining parts of the patterned hardmask and temporary layers to an other hard mask layer.

3. The method of claim 2, further comprising subsequently processing the substrate through the other hard mask layer.

4. The method of claim 2, wherein processing the substrate comprises etching the substrate.

5. The method of claim 1, further comprising reducing widths of elements in the patterned hardmask and temporary layers by isotropically etching the elements before forming spacers.

6. The method of claim 1, wherein the temporary layer comprises amorphous carbon.

7. The method of claim 1, wherein the temporary layer comprises transparent carbon.

8. The method of claim 6, wherein the hard mask layer comprises a dielectric anti-reflective coating.

9. The method of claim 8, wherein the spacers comprise silicon oxide.

10. The method of claim 8, wherein the spacers and the temporary layer directly overlie an etch stop layer comprising silicon nitride.

11. The method of claim 1, wherein preferentially removing the exposed parts of the patterned hardmask and temporary layers comprises forming free-standing spacers directly over an array region of the substrate.

12. The method of claim 11, wherein the freestanding spacers have a pitch below a resolution limit of a photolithographic technique used for patterning the first photoresist layer.

13. The method of claim 1, wherein the spacers extend in spaced, generally parallel relation to one another at least between first and second spaced planes extending perpendicular to the spacers.

14. A method for forming an integrated circuit, comprising:

patterning a selectively definable layer to simultaneously define array mask elements in an array region and periphery mask elements in a periphery region of a partially fabricated integrated circuit;

subsequently performing pitch multiplication in the array region to form a plurality of free-standing spacers; and

simultaneously transferring a pattern defined at least partly by the free-standing spacers and the periphery mask elements to a substrate.

15. The method of claim 14, wherein performing pitch multiplication comprises:

forming spacers on sidewalls of the array and periphery mask elements; and

preferentially removing the array mask elements, thereby forming the free-standing spacers.

16. The method of claim 15, wherein forming spacers on sidewalls comprises:

depositing a blanket layer of spacer material on the array and periphery mask elements; and

anisotropically etching the blanket layer to define the spacers.

17. The method of claim 15, wherein performing pitch multiplication further comprises, after forming spacers on sidewalls and before preferentially removing the array mask elements:

depositing a layer of protective material on the spacers and the array and periphery mask elements; and

patterning the protective material to expose the array mask elements.

18. The method of claim 17, wherein depositing the layer of protective material comprises depositing photoresist, wherein patterning the protective material comprises performing photolithography.

19. The method of claim 17, wherein patterning the protective material comprises removing some of the protective material to expose all spacers in the array region.

20. The method of claim 16, wherein depositing the blanket layer comprises performing chemical vapor deposition.

21. The method of claim 14, wherein simultaneously transferring the pattern forms electrical devices in the array and periphery regions of the partially fabricated integrated circuit.

22. The method of claim 21, wherein the electrical devices are electrical interconnects.

23. The method of claim 22, wherein simultaneously transferring the pattern forms landing pads directly contacting the interconnects.

24. The method of claim 22, wherein simultaneously transferring the pattern forms pitch-multiplied interconnects in contact with non-pitch multiplied interconnects.

25. The method of claim 14, wherein patterning the selectively definable layer comprises patterning a photoresist layer.

26. A method for fabricating an integrated circuit, comprising:

providing a substrate with an overlying photoresist layer;

patterning the photoresist layer using a photolithographic technique to form a photoresist pattern comprising photoresist material separated by voids, the photoresist material and voids extending over an array region and a periphery region of the integrated circuit;

transferring the photoresist pattern to an underlying temporary layer to form a temporary layer pattern;

subsequently shrinking elements in the temporary layer pattern in both the array and the periphery regions;

depositing a blanket layer of spacer material over the temporary layer elements; and

etching the blanket layer to form spacers at sides of the temporary layer elements.

27. The method of claim 26, further comprising:

protecting at least part of the temporary layer pattern in the periphery region with a protective material and exposing at least part of the temporary layer pattern in the array region; and

selectively removing exposed temporary layer material to from free-standing spacers in the array region.

28. The method of claim 27, further comprising:

removing the protective material; and

processing a substrate through the mask pattern defined by the remaining parts of the temporary layer and the free-standing spacers.

29. The method of claim 28, wherein processing the substrate comprises transferring the mask pattern to the substrate.

30. The method of claim 29, wherein transferring the mask pattern comprises forming parts of a memory cell array and parts of logic circuitry in a partially formed memory device.

31. The method of claim 29, wherein transferring the mask pattern comprises etching the pattern into a hard mask layer and subsequently etching the substrate.

32. The method of claim 26, wherein transferring the photoresist pattern to an underlying temporary layer comprises etching a hard mask layer and subsequently etching the temporary layer.

33. The method of claim 32, wherein depositing the blanket layer of spacer material comprises depositing spacer material over hard mask material and temporary layer material.

34. The method of claim 26, wherein patterning the photoresist layer comprises performing photolithography with light having a wavelength chosen from the group consisting of 13.7 nm, 157 nm, 193 nm, 248 nm and 365 nm wavelength light.

35. The method of claim 26, wherein the temporary layer is formed of amorphous carbon.

36. The method of claim 35, wherein the spacer material is silicon nitride.

37. A partially fabricated integrated circuit, comprising:

a plurality of mask elements overlying a hard mask layer, the hard mask layer overlying a substrate;

spacers disposed on sidewalls of the mask elements; and

a protective layer directly overlying some of the spacers and some of the mask elements, the protective layer leaving others of the spacers and others of the mask elements exposed.

38. The partially fabricated integrated circuit of claim 37, wherein the protective layer is a patterned layer, wherein spacers in an array region of the partially fabricated integrated circuit are exposed.

39. The partially fabricated integrated circuit of claim 38, wherein some surfaces of the mask elements in a periphery region of the partially fabricated integrated circuit are exposed.

40. The partially fabricated integrated circuit of claim 37, wherein the mask elements are disposed in an array and a periphery region of the partially fabricated integrated circuit.

41. The partially fabricated integrated circuit of claim 37, wherein the mask elements comprise a hard mask layer overlying a temporary layer, wherein the hard mask layer and the temporary layer are selectively etchable relative to the spacers.

42. The partially fabricated integrated circuit of claim 37, wherein the mask elements are formed of amorphous carbon.

43. The partially fabricated integrated circuit of claim 37, wherein the protective layer comprises photoresist.

44. A partially fabricated integrated circuit, comprising:

a plurality of pairs of spacers over a substrate, wherein spacers constituting each pair of spacers are separated by a selectively etchable material; and

a patterned photoresist layer overlying some of the pairs of spacers, wherein photoresist overlies at least some spacers in a periphery or interface region of the partially fabricated integrated circuit and wherein spacers in an array region of the partially fabricated integrated circuit are exposed.

45. The partially fabricated integrated circuit of claim 44, wherein the selectively etchable material is amorphous carbon.

46. The partially fabricated integrated circuit of claim 45, wherein the spacers comprise a material selected from the group consisting of silicon, silicon nitride and silicon oxide.

47. The partially fabricated integrated circuit of claim 44, wherein the patterned photoresist layer is formed of photoresist compatible with 13.7 nm, 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems or electron beam lithographic systems.

48. The partially fabricated integrated circuit of claim 44, wherein the partially fabricated integrated circuit is a partially formed memory device.

49. The partially fabricated integrated circuit of claim 48, wherein the memory device is a NAND flash memory.

50. The partially formed integrated circuit of claim 44, wherein the plurality of pairs of spacers correspond to features of a memory array.

51. The partially formed integrated circuit of claim 44, wherein the partially formed integrated circuit is a partially formed computer processor.

52. The partially formed integrated circuit of claim 44, wherein the plurality of pairs of spacers correspond to features of a logic array.

53. A partially fabricated integrated circuit, comprising:

a plurality of pairs of free-standing spacers disposed over an array region of the partially fabricated integrated circuit; and

an other plurality of other pairs of spacers on a same level as the plurality of pairs of spacers, wherein spacers of the other pairs of spacers are disposed on sidewalls of a temporary material selectively etchable relative to the other pairs of spacers,

wherein one or more openings are provided in the temporary material.

54. The partially fabricated integrated circuit of claim 53, wherein the one or more openings are disposed in periphery areas of the partially fabricated integrated circuit.

55. The partially fabricated integrated circuit of claim 54, wherein the one or more openings have a desired shape and placement of interconnects in the periphery areas of the partially fabricated integrated circuit.

56. The partially fabricated integrated circuit of claim 53, wherein the free-standing spacers have a separation of less than about 100 nm and the other pairs of spacers have a separation of greater than about 100 nm.

57. The partially fabricated integrated circuit of claim 53, wherein the pairs of free-standing spacers extend in spaced, generally parallel relation to one another at least between first and second spaced planes extending perpendicular to the pairs of free-standing spacers.

58. The partially fabricated integrated circuit of claim 57, wherein the other pairs of spacers extend in spaced, generally parallel relation to one another at least between first and second spaced planes extending perpendicular to the other pairs of spacers.

59. The partially fabricated integrated circuit of claim 53, wherein the temporary material is amorphous carbon.