Method and apparatus for semiconductor device and semiconductor memory device

• US 20080070390A1
• Filed: 10/30/2007
• Published: 03/20/2008
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Chih-Hsin Wang
• Inventors: Wang, Chih-Hsin
• Granted Patent: US 7,824,981 B2
• Time in Patent Office: Days
• US Class Current: 438/514
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method comprises providing a first conductive region, arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region, arranging a third region adjacent to and insulated from the second conductive region, and adjusting mechanical stress to at least one of the first conductive region and the second conductive region.

Claims

1. A method comprising:

providing a first conductive region;

arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region;

arranging a third region adjacent to and insulated from the second conductive region; and

adjusting mechanical stress to at least one of the first conductive region and the second conductive region.

2. The method of claim 1 further comprising:

arranging a charge injection filter of the dielectric region between the first and the second conductive regions;

controlling transport of charge carriers of one polarity type from the first conductive region through the second conductive region to the third region using the charge injection filter; and

blocking transport of charge carriers of an opposite polarity type from the second conductive region to the first conductive region using the charge injection filter.

3. The method of claim 1 wherein the mechanical stress includes one of a tensile stress and a compressive stress.

4. The method of claim 1 wherein the mechanical stress produces strain in a direction substantially parallel to a direction of charge carrier transport in the second conductive region.

5. The method of claim 1 wherein the second conductive region comprises a material selected from the group consisting of Pt, Au, W, Mo, Ru, Ta, TaN, TiN, silicide, n+ polysilicon, p+ polysilicon, n+ poly SiGe, porous silicon, and p+ poly SiGe.

6. The method of claim 1 wherein the mechanical stress is adjusted using a strain source, and wherein the strain source comprises a material selected from the group consisting of nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.

7. The method of claim 1 wherein the mechanical stress is adjusted using a strain source, and wherein the strain source comprises dislocation loops in at least one of the first and the second conductive regions.

8. The method of claim 2 wherein the arranging the charge injection filter includes:

arranging a first dielectric adjacent to the second conductive region; and

arranging a second dielectric adjacent to the first conductive region,

wherein the first dielectric has an energy band gap narrower than an energy band gap of the second dielectric.

9. The method of claim 8 wherein a product of a dielectric constant of the first dielectric and a thickness of the second dielectric is greater than a product of a dielectric constant of the second dielectric and a thickness of the first dielectric.

10. The method of claim 8 wherein the second dielectric comprises oxide, and the first dielectric comprises material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

11. The method of claim 8 wherein the second dielectric comprises oxynitride, and the first dielectric comprises a material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, HfO₂⁻

SiO₂, and alloys formed thereof.

12. The method of claim 1 wherein the third region comprises a material selected from the group consisting of conductive material, nano-particles, and dielectrics.

13. A method comprising,

providing a first conductive region having charge carriers for ballistic transport;

arranging a second conductive region adjacent to and insulated from the first conductive region to control the ballistic transport of the charge carriers;

arranging a third region adjacent to and insulated from the second conductive region,

wherein the third region receives the charge carriers with an injection efficiency for the ballistic transport; and

adjusting mechanical stress in at least one of the first conductive region and the second conductive region to enhance the injection efficiency of the ballistic transport.

14. The method of claim 13 further comprising adjusting the mechanical stress using a strain source, wherein the strain source comprises a strain material contacting at least one of the first and second conductive regions.

15. The method of claim 13 further comprising adjusting the mechanical stress using a strain source, wherein the strain source comprises dislocation loops in at least one of the first and second conductive regions.

16. The method of claim 13 wherein the mechanical stress has a magnitude of stress level in the range of about 60 MPa to about 2 GPa.

17. The method of claim 13 wherein the mechanical stress is controlled by ion implantation.

18. The method of claim 17 wherein the ion implantation comprises implanting a material selected from the group consisting of Ge, Si, As, and nitrogen.

19. A method comprising:

providing a first conductive region having a population of charge carriers;

arranging a second conductive region adjacent to and insulated from the first conductive region for controlling transport of charge carriers from the first conductive region;

arranging a third region adjacent to and insulated from the second conductive region,

wherein the third region receives the charge carriers; and

adjusting mechanical stress in at least one of the first conductive region and the second conductive region.

20. The method of claim 19 further comprising adjusting the mechanical stress to alter the population of charge carriers in the first conductive region to enhance injection efficiency.

21. The method of claim 19 wherein the charge carriers in the second conductive region have a mean-free-path, and wherein the method further comprises adjusting the mechanical stress to increase the mean-free-path in the second conductive region to enhance injection efficiency.