SEMICONDUCTOR DEVICES AND METHODS WITH BILAYER DIELECTRICS

• US 20080070395A1
• Filed: 09/15/2006
• Published: 03/20/2008
• Est. Priority Date: 09/15/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Peng-Fu, Tao, Hun-Jan, Hou, Yong-Tian, Ying, Jin, Yen, Fong-Yu, Hung, Cheng-Lung, Chang, Vencent S.
• Granted Patent: US 7,531,399 B2
• Time in Patent Office: Days
• US Class Current: 438/591
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a first dielectric layer of a first high-k material above the substrate, the first high-k material selected from the group consisting of HfO₂, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO;

forming a second dielectric layer of a second high-k material above the first dielectric layer, the second material being different than the first material and selected from the group consisting of HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and

forming a gate structure above the second dielectric layer.

2. The method of claim 1 further comprising forming an interfacial layer above the substrate prior to forming the first dielectric layer.

3. The method of claim 2 wherein the interfacial layer has a thickness of less than 1 nm.

4. The method of claim 3 wherein the interfacial layer is formed of SiO₂.

5. The method of claim 2 wherein the interfacial layer is formed by rapid thermal oxidation.

6. The method of claim 5 wherein the second dielectric layer has a thickness between 0.3-2.0 nm.

7. The method of claim 1 wherein the first and second dielectric layers are each formed by a method selected from the group consisting of atomic layer deposition (ALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), and combinations thereof.

8. The method of claim 1 further comprising performing a nitridation technique on the first dielectric layer prior to forming the second dielectric layer.

9. The method of claim 8 wherein the nitridation technique includes plasma nitridation.

10. The method of claim 8 wherein the nitridation technique includes thermal nitridation.

11. The method of claim 8 further comprising performing a post deposition anneal on the first dielectric layer after performing the nitridation technique and before forming the second dielectric layer.

12. The method of claim 11 wherein the post deposition anneal is performed at a temperature between 400-1200°

Celsius.

13. The method of claim 12 wherein the post deposition anneal is performed with an inert gas selected from the group consisting of N₂, O₂, H₂, D₂, NH₃, Ar, and combinations thereof.

14. The method of claim 1 further comprising implanting ions selected from the group comprising N, O, and Si into the first dielectric layer before forming the second dielectric layer.

15. The method of claim 14 further comprising performing a post deposition anneal on the first dielectric layer after implanting ions and before forming the second dielectric layer.

16. The method of claim 1 wherein the gate structure is formed of a metal.

17. The method of claim 16 wherein the metal is selected from the group consisting of TaC, TaN, TaSi, TaSiN, Ru, Mo₂N, IrSi₃, and Pt.

18. The method of claim 17 wherein the gate structure is formed by a method selected from the group consisting of physical vapor deposition (PVD), atomic layer deposition (ALD), and metal-organic chemical vapor deposition (MOCVD).

19. A method of forming a semiconductor device, comprising:

providing a substrate;

forming an interfacial layer above the substrate;

forming a first dielectric layer of a first high-k material above the interfacial layer;

performing a nitridation technique;

performing an anneal;

forming a second dielectric layer of a second high-k material above the first dielectric layer after performing the nitridation technique and after performing the anneal; and

forming a metal gate structure above the second dielectric layer.

20. The method of claim 19 wherein the interfacial layer is formed of SiO2;

wherein the first dielectric layer is formed of HfSiO;

wherein the second dielectric layer is formed of HfO2; and

wherein the metal gate is formed of TaC.

21. A semiconductor device comprising:

a substrate;

a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO₂, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO;

a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second material being different than the first material and selected from the group consisting of HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and

a metal gate formed over the second dielectric layer.

22. The semiconductor device of claim 21 further comprising an interfacial layer positioned between the substrate and the first dielectric layer.

23. The semiconductor device of claim 22 wherein the interfacial layer has a thickness less than 1 nm.

24. The semiconductor device of claim 23 wherein the interfacial layer is formed of SiO₂.

25. The semiconductor device of claim 21 wherein the metal gate is formed of a metal selected from the group consisting of TaC, TaN, TaSi, TaSiN, Ru, Mo₂N, IrSi₃, and Pt.

26. The semiconductor device of claim 25 wherein the first dielectric layer has a thickness between 1-10 nm.

27. The semiconductor device of claim 26 wherein the second dielectric layer has a thickness between 0.3-2.0 nm.

28. The semiconductor device of claim 27

wherein the first dielectric layer is positioned between the substrate and the second dielectric layer;

and

wherein the second dielectric layer is positioned between the first dielectric layer and the metal gate.

29. The semiconductor device of claim 28

wherein the first material is HfSiON;

wherein the second material is HfO₂; and

wherein the metal gate is formed of TaC.

30. The semiconductor device of claim 29 further comprising an interfacial layer formed of SiO₂ positioned between the substrate and the first dielectric layer.