Instruction and logic for performing a dot-product operation

• US 20080071851A1
• Filed: 09/20/2006
• Published: 03/20/2008
• Est. Priority Date: 09/20/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Desylva, Chuck, Seconi, Mark, Zohar, Ronen, Buxton, Mark, Chennupaty, Srinivas, Parthasarathy, Rajesh
• Application Number:
  US11/524,852
• Publication Number:
  US 20080071851A1
• Time in Patent Office: Days
• US Class Current: 708/626
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions

Abstract

Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Claims

1. A machine-readable medium having stored thereon an instruction, which if executed by a machine causes the machine to perform a method comprising:

determining a dot-product result of at least two operands, each having a plurality of packed values of a first datatype;

storing the dot-product result.

2. The machine-readable medium of claim 1, wherein the first datatype is an integer datatype.

3. The machine-readable medium of claim 1, wherien the first datatype is a floating point datatype.

4. The machine-readable medium of claim 1, wherein the at least two operands each have only two packed values.

5. The machine-readable medium of claim 1, wherein the at least two operands each have only four packed values.

6. The machine-readable medium of claim 1, wherein each of the plurality of packed values is a single-precision value and is to be represented by 32 bits.

7. The machine-readable medium of claim 1, wherein each of the plurality of packed values is a double-precision value and is to be represented by 64 bits.

8. The machine-readable medium of claim 1, wherein the at least two operands and the dot-product result are to be stored in at least two registers to store up to 128 bits of data.

9. An apparatus comprising:

a first logic to perform a single-instruction-multiple-data (SIMD) dot-product instruction on at least two packed operands of a first datatype.

10. The apparatus of claim 9, wherein the SIMD dot-product instruction includes a source operand indicator, a destination operand indicator, and at least one immediate value indicator.

11. The apparatus of claim 10, wherein the source operand indicator includes an address of a source register having a plurality of elements to store a plurality of packed values.

12. The apparatus of claim 11, wherein the destination operand indicator includes an address of a destination register having a plurality of elements to store a plurality of packed values.

13. The apparatus of claim 12, wherein the immediate value indicator includes a plurality of control bits.

14. The apparatus of claim 9, wherein the at least two packed operands are each double-precision integers.

15. The apparatus of claim 9, wherein the at least two packed operands are each double precision floating point values.

16. The apparatus of claim 9, wherein the at least two packed operands are each single precision integers.

17. The apparatus of claim 9, wherein the at least two packed operands are each single precision floating point values.

18. A system comprising:

a first memory to store a single-instruction-multiple-data (SIMD) dot-product instruction;

a processor coupled to the first memory to perform the SIMD dot-product instruction.

19. The system of claim 18, wherein the SIMD dot-product instruction includes a source operand indicator, a destination operand indicator, and at least one immediate value indicator.

20. The system of claim 19, wherein the source operand indicator includes an address of a source register having a plurality of elements to store a plurality of packed values.

21. The system of claim 20, wherein the destination operand indicator includes an address of a destination register having a plurality of elements to store a plurality of packed values.

22. The system of claim 21, wherein the immediate value indicator includes a plurality of control bits.

23. The system of claim 18, wherein the at least two packed operands are each double-precision integers.

24. The system of claim 18, wherein the at least two packed operands are each double precision floating point values.

25. The system of claim 18, wherein the at least two packed operands are each single precision integers.

26. The apparatus of claim 18, wherein the at least two packed operands are each single precision floating point values.

27. A method comprising:

multiplying a first data element of a first packed operand and a first data element of a second packed operand to generate a first product;

multiplying a second data element of the first packed operand and a second data element of the second packed operand to generate a second product;

adding the first product to the second product to generate a dot-product result.

28. The method of claim 27, further comprising multiplying a third data element of the first packed operand and a third data element of the second packed operand to generate a third product.

29. The method of claim 28, further comprising multiplying a fourth data element of the first packed operand and a fourth data element of the second packed operand to generate a fourth product.

30. A processor comprising:

a source register to store a first packed operand, including a first and second data value;

a destination register to store a second packed operand, including a third and fourth data value;

logic to perform a single-instruction-multiple-data (SIMD) dot-product instruction according to a control value indicated by the dot-product instruction, the logic comprising a first multiplier to multiply the first and third data values to generate a first product, a second multiplier to multiply the second and fourth data values to generate a second product, the logic further including at least one adder to add to the first and second product to produce at least one sum.

31. The processor of claim 30, wherein the logic further includes a first multiplexer to select between the first product and a null value, depending upon a first bit of the control value.

32. The processor of claim 31, wherein the logic further includes a second multiplexer to select between the second product and a null value, depending upon a second bit of the control value.

33. The processor of claim 32, wherein the logic further includes a third multiplexer to select between the sum and a null value to be stored in a first element of the destination register.

34. The processor of claim 33, wherein the logic further includes a fourth multiplexer to select between the sum and a null value to be stored in a second element of the destination register.

35. The processor of claim 30, wherein the first, second, third, and fourth data values are 64 bit integer values.

36. The processor of claim 30, wherein the first, second, third, fourth data values are 64 bit floating point values.

37. The processor of claim 30, wherein the first, second, third, and fourth data values are 32 bit integer values.

38. The processor of claim 30, wherein the first, second, third, and fourth data values are 32 bit floating point values.

39. The processor of claim 30, wherein the source and destination registers are to store at least 128 bits of data.