Software reconfigurable digital phase lock loop architecture
First Claim
1. A processor for use in a software based phase locked loop (PLL), comprising:
- a first adder/subtractor operative to receive input data;
a shifter operative to shift the output of said first adder/subtractor by a predetermined amount;
a second adder/subtractor operative to receive the output of said shifter;
a latch operative to store the output of said second adder/subtractor;
a plurality of data paths connecting said first adder/subtractor, said shifter, said second adder/subtractor and said latch, said plurality of data paths configurable in accordance with one or more control signals; and
wherein said processor having an instruction set for controlling said first adder/subtractor, said shifter, said second adder/subtractor, said latch and said plurality of data paths.
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Accused Products
Abstract
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
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Citations
45 Claims
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1. A processor for use in a software based phase locked loop (PLL), comprising:
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a first adder/subtractor operative to receive input data; a shifter operative to shift the output of said first adder/subtractor by a predetermined amount; a second adder/subtractor operative to receive the output of said shifter; a latch operative to store the output of said second adder/subtractor; a plurality of data paths connecting said first adder/subtractor, said shifter, said second adder/subtractor and said latch, said plurality of data paths configurable in accordance with one or more control signals; and wherein said processor having an instruction set for controlling said first adder/subtractor, said shifter, said second adder/subtractor, said latch and said plurality of data paths. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A processor for use in a software based phase locked loop (PLL), comprising:
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one or more computation units optimized for performing computations within a phase locked loop, wherein said one or more computation units are time-shared among all phase locked loop computations; data memory coupled to said one or more computation units; instruction memory coupled to said one or more computation units and operative to store instructions for implementing said phase locked loop, said instructions part of an instruction set; and a decoder operative to generate one or more control signals for controlling the operation of said one or more computation units. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A processor based phase locked loop (PLL), comprising:
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an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto; a processor operative to generate said tuning command, said processor comprising; a reconfigurable calculation unit (RCU) operative to perform atomic operations required to implement said phase locked loop; data memory coupled to said reconfigurable calculation unit for storing phase locked loop state information; program memory coupled to said reconfigurable calculation unit for storing a plurality of instructions that when executed on said processor implement said phase locked loop; and said processor having an instruction set, wherein each instruction is operative to perform an atomic operation of said phase locked loop. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A radio, comprising:
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a transmitter coupled to an antenna, said transmitter comprising a software based phase locked loop (PLL), said phase locked loop comprising; an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto; a processor operative to generate said tuning command, said processor comprising; a reconfigurable calculation unit (RCU) operative to perform atomic operations required to implement said phase locked loop; data memory coupled to said reconfigurable calculation unit for storing phase locked loop state information; program memory coupled to said reconfigurable calculation unit for storing a plurality of instructions that when executed on said processor implement said phase locked loop; said processor having an instruction set, wherein each instruction is operative to perform an atomic operation of said phase locked loop; a receiver coupled to said antenna; and a baseband processor coupled to said transmitter and said receiver. - View Dependent Claims (42, 43, 44, 45)
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Specification