METHODS AND APPARATUS TO SELF-INITIALIZE A PROCESSOR

• US 20080072027A1
• Filed: 09/19/2006
• Published: 03/20/2008
• Est. Priority Date: 09/19/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Rothman, Michael A., Doran, Mark S.
• Granted Patent: US 7,673,126 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

Methods and apparatus are disclosed to self-initialize a processor. An example method disclosed herein detects a processor reset, receives initialization instructions from a core zone, establishes a core zone boundary, executes received initialization instructions, and publishes a data structure, the data structure comprising state information. Other embodiments are described and claimed.

Claims

1. A method of self-initializing a processor, the method comprising:

detecting a processor reset;

receiving initialization instructions from a core zone;

establishing a core zone boundary;

executing received initialization instructions; and

publishing a data structure, the data structure comprising state information.

2. A method as defined in claim 1, wherein detecting the processor reset comprises detecting at least one of a power-on state or a chipset reset signal.

3. A method as defined in claim 1, further comprising receiving initialization instructions from at least one of a processor memory, a flash memory, a read only memory (ROM), or a random access memory (RAM).

4. A method as defined in claim 3, wherein the at least one of the processor memory, the flash memory, the ROM, or the RAM resides within the core zone.

5. A method as defined in claim 4, wherein the initialization instructions prevent execution of at least one of software or firmware external to the core zone.

6. A method as defined in claim 1, wherein the initialization instructions execute on at least one device in the core zone.

7. A method as defined in claim 6, wherein the at least one device in the core zone comprises at least one of the processor, a memory controller, or an input/output (I/O) controller.

8. A method as defined in claim 1, further comprising handing-off the processor to at least one of an operating system (OS), a basic input/output system (BIOS) process, or an original equipment manufacturer (OEM) system.

9. A method as defined in claim 8, wherein the processor is handed-off in at least one of real mode, protected mode, or long mode.

10. A method as defined in claim 1, further comprising generating a device list corresponding to a plurality of devices in the core zone.

11. A method as defined in claim 10, further comprising generating the data structure for each one of the plurality of devices in the core zone.

12. An apparatus to self-initialize a processor, the apparatus comprising:

a core zone comprising at least one processor;

a core initializer to initialize the at least one processor in the core zone; and

a plurality of data structures to provide state information for the at least one processor in the core zone.

13. An apparatus as defined in claim 12, wherein the core zone comprises at least one of a memory controller, an input/output (I/O) controller, or at least one processor chipset.

14. An apparatus as defined in claim 12, wherein the core initializer comprises a reset detector to determine at least one of a computer platform power-up or a computer platform reset request.

15. An apparatus as defined in claim 12, wherein the core initializer comprises a core initializer and a memory, the core initializer to execute initialization instructions stored on the memory.

16. An apparatus as defined in claim 15, further comprising a platform memory external to the core zone, the core initializer initializing the platform memory.

17. An apparatus as defined in claim 12, wherein the core initializer comprises a core interface to provide state information to non-core zone entities.

18. An apparatus as defined in claim 17, wherein the non-core zone entities comprise at least one of a basic input and output system (BIOS), an original equipment manufacturer (OEM) application, or a firmware application.

19. An apparatus as defined in claim 17, wherein the core interface comprises a plurality of data structures, each one of the plurality of data structures comprising a plurality of core zone state information.

20. An article of manufacturing storing machine readable instructions which, when executed, cause a machine to:

detect a processor reset;

receive initialization instructions from a core zone;

establish a core zone boundary;

execute received initialization instructions; and

publish a data structure, the data structure comprising state information.

21. An article of manufacture as defined in claim 20, wherein the machine readable instructions cause the machine to detect at least one of a power-on state or a chipset reset signal.

22. An article of manufacture as defined in claim 20, wherein the machine readable instructions cause the machine to receive initialization instructions from at least one of a processor memory, a flash memory, a read only memory (ROM), or a random access memory (RAM).

23. An article of manufacture as defined in claim 22, wherein the machine readable instructions cause the machine to prevent execution of at least one of software or firmware external to the core zone.

24. An article of manufacture as defined in claim 20, wherein the machine readable instructions cause the machine to execute the initialization instructions on at least one device in the core zone.

25. An article of manufacture as defined in claim 20, wherein the machine readable instructions cause the machine to hand-off the processor to at least one of an operating system (OS), a basic input and output system (BIOS) process, or an original equipment manufacturer (OEM) system.

26. An article of manufacture as defined in claim 25, wherein the machine readable instructions cause the machine to hand-off the processor in at least one of real mode, protected mode, or long mode.

27. An article of manufacture as defined in claim 20, wherein the machine readable instructions cause the machine to generate a device list corresponding to a plurality of devices in the core zone.

28. An article of manufacture as defined in claim 27, wherein the machine readable instructions cause the machine to generate a data structure for each one of the plurality of devices in the core zone.