Allowable bit errors per sector in memory devices

• US 20080072119A1
• Filed: 08/31/2006
• Published: 03/20/2008
• Est. Priority Date: 08/31/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rozman, Rodney
• Application Number:
  US11/515,048
• Publication Number:
  US 20080072119A1
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A method of reading a page from a memory array, wherein the page includes a plurality of sector, determining whether each of the plurality of sectors includes an allowable number of errors, and providing a success indicator if each of the plurality of sectors includes an allowable number of errors.

Claims

1. A method comprising:

reading a page from a memory array, wherein the page includes a plurality of sectors;

determining whether each of the plurality of sectors includes an acceptable number of errors; and

providing a success indicator if each of the plurality of sectors includes the acceptable number of errors.

2. The method of claim 1, wherein reading the page from the memory array occurs while performing a program verify operation.

3. The method of claim 1, wherein determining whether each of the plurality of sectors includes the acceptable number of errors comprises comparing a total number of errors in each sector with a maximum number of acceptable errors for each sector.

4. The method of claim 3, wherein the maximum number of acceptable errors for each sector is equal to the number of errors in each sector that may be corrected using ECC.

5. The method of claim 3, wherein the maximum number of acceptable errors for each sector is determined by a user.

6. The method of claim 1, wherein providing the success indicator comprises writing a value to a status register.

7. The method of claim 1, further comprising providing a failure indicator if at least one of the plurality of sectors includes greater than the acceptable number of errors.

8. The method of claim 1, further comprising performing an ECC operation to correct up to the acceptable number of errors in each of the plurality of sectors.

9. An apparatus comprising:

a memory array; and

logic coupled to the memory array, the logic to determine a number of errors in each of a plurality of sectors in a page read from the memory array and to indicate if the number of errors in each of the plurality of sectors is an acceptable number of errors.

10. The apparatus of claim 9, wherein the logic includes a comparator to compare the number of errors in each of the plurality of sectors with a maximum number of acceptable errors for each sector.

11. The apparatus of claim 10, wherein the maximum number of acceptable errors for each sector is equal to the number of errors in each sector that may be corrected using ECC.

12. The apparatus of claim 10, wherein the maximum number of acceptable errors for each sector is determined by a user.

13. The apparatus of claim 9, wherein the logic is further to indicate if the number of errors in each of the plurality of sectors is less than or equal to the acceptable number of errors by writing a value to a status register.

14. The apparatus of claim 9, wherein the logic is further to indicate if the number of errors in each of the plurality of sectors is greater than the acceptable number of errors.

15. A system comprising:

an interconnect;

a processor coupled to the interconnect;

a wireless interface coupled to the interconnect; and

a memory device coupled to the interconnect, wherein the memory device includes a memory array and logic coupled to the memory array, the logic to determine a number of errors in each of a plurality sectors in a page read from the memory array and to indicate if the number of errors in each of the plurality of sectors is an acceptable number of errors.

16. The system of claim 15, wherein the memory device is a NAND flash memory device.

17. The system of claim 15, further comprising an error control coding (ECC) module coupled to the interconnect.