COMMUNICATIONS DIGITAL SIGNAL PROCESSOR AND DIGITAL SIGNAL PROCESSING METHOD

• US 20080072129A1
• Filed: 10/30/2007
• Published: 03/20/2008
• Est. Priority Date: 06/30/1997
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: STONE, Kevin, OKAMOTO, Minoru, YAMANAKA, Ryutaro, KABUO, Hideyuki, SUZUKI, Hidetoshi
• Application Number:
  US11/929,126
• Publication Number:
  US 20080072129A1
• Time in Patent Office: Days
• US Class Current: 714/796
• CPC Class Codes: H03M 13/3961 Arrangements of methods for branch or transition metric calculation
• CPC Class Codes: H03M 13/4107 implementing add, compare, select [ACS] operations
• CPC Class Codes: H03M 13/4169 using traceback H03M13/4192 takes precedence
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H03M 13/6563 Implementations using multi-port memories
• CPC Class Codes: H03M 13/6569 Implementation on processors, e.g. DSPs, or software implementations

Abstract

A digital signal processor includes an instruction executer configured to execute instructions. The instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The instruction executer outputs a processed data including the first minimum data and the second minimum data. A bit length of the first minimum data is equal to n bits in length. A bit length of the second minimum data is equal to n bits in length. A bit length of the processed data is equal to at least 2n bits in length.

Claims

1. A digital signal processor, comprising:

an instruction executer configured to execute instructions;

wherein the instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data;

wherein the instruction executer outputs a processed data including the first minimum data and the second minimum data;

wherein a bit length of the first minimum data is equal to n bits in length;

wherein a bit length of the second minimum data is equal to n bits in length; and

wherein a bit length of the processed data is equal to at least 2n bits in length.

2. The digital signal processor according to claim 1, further comprising:

an instruction fetcher that fetches instructions; and

a decoder that decodes the instructions fetched by the instruction fetcher.

3. The digital signal processor according to claim 2,

wherein the digital signal processor provides the processed data by one instruction.

4. The digital signal processor according to claim 3,

wherein the digital signal processor provides the first data when the first data is equal to the second data, and provides the third data when the third data is equal to the fourth data.

5. A digital signal processor, comprising:

an instruction executer configured to execute instructions;

wherein the instruction executer is used to determine a first minimum data of a first data and a second data, in a single cycle in which a second minimum data of a third data and a fourth data is also determined, and

wherein the instruction executer is configured to perform a register-register operation.

6. The digital signal processor according to claim 5, further comprising:

an instruction fetcher that fetches instructions; and

a decoder that decodes the instructions fetched by the instruction fetcher.

7. The digital signal processor according to claim 6,

wherein the instruction executer outputs a processed data including the first minimum data and the second minimum data, and

wherein the digital signal processor provides the processed data by one instruction.

8. The digital signal processor of claim 7,

wherein the instruction executer is configured to perform a first addition, a second addition, a third addition and a fourth addition in parallel.

9. The digital signal processor according to claim 8,

wherein the digital signal processor provides the first data when the first data is equal to the second data, and provides the third data when the third data is equal to the fourth data.

10. The digital signal processor according to claim 9,

wherein the digital signal processor provides the first minimum data as a high part of the processed data, and

wherein the digital signal processor provides the second minimum data as a low part of the processed data.

11. The digital signal processor according to claim 8, further comprising:

a plurality of registers, including a first register and a second register, for storing data,

wherein the first register stores a result of determining the first minimum data, and

wherein the second register stores a result of determining the second minimum data.