Processor with hardware solution for priority inversion
First Claim
1. A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts, said method comprising:
- providing a plurality of context control registers, each of said context control registers being associated with a corresponding one context of said plurality of contexts for controlling execution of said corresponding context;
providing a plurality of sets of hardware registers, each set of said plurality of sets of hardware registers corresponding to one context of said plurality of contexts; and
utilizing said plurality of context control registers and said plurality of sets of hardware registers to prevent priority inversion.
3 Assignments
0 Petitions
Accused Products
Abstract
A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts is provided. The method comprises: providing a plurality of context control registers with each context control register being associated with a corresponding one context for controlling execution of the context; providing a plurality of sets of hardware registers, each set corresponding to one context of the plurality of contexts; and utilizing the plurality of context control registers and said plurality of sets of hardware registers to prevent priority inversion.
-
Citations
13 Claims
-
1. A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts, said method comprising:
-
providing a plurality of context control registers, each of said context control registers being associated with a corresponding one context of said plurality of contexts for controlling execution of said corresponding context; providing a plurality of sets of hardware registers, each set of said plurality of sets of hardware registers corresponding to one context of said plurality of contexts; and utilizing said plurality of context control registers and said plurality of sets of hardware registers to prevent priority inversion. - View Dependent Claims (2, 3)
-
-
4. A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts, said method comprising:
-
providing a plurality of context control registers, each of said context control registers being associated with a corresponding one context of said plurality of contexts for controlling execution of said corresponding context; providing a plurality of sets of hardware registers, each set of said plurality of sets of hardware registers corresponding to one context of said plurality of contexts; and selectively operating said plurality of sets of hardware registers in conjunction with said plurality of context control registers to provide priority inheritance or priority ceiling to prevent priority inversion. - View Dependent Claims (5, 6)
-
-
7. A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts, said method comprising:
-
providing a plurality of context control registers, each of said context control registers being associated with a corresponding one context of said plurality of contexts for controlling execution of said corresponding context; providing a plurality of sets of hardware registers, each set of said plurality of sets of hardware registers corresponding to one context of said plurality of contexts; providing in each of said sets of hardware registers one register having a field that is conditionally writeable; operating each said one register such that a second context of said plurality of contexts will attempt to write a value to said field to claim a value; operating said one register such that if a write of a predetermined value to said field is successful said second context takes a claim and may proceed to execute; operating said one register such that if said write of said predetermined value to said field is not successful said second context will pend until said first context completes execution; and loaning the priority of said second context to said first context while said first context is executing. - View Dependent Claims (8, 9, 10, 11)
-
-
12. A processor system having an operating system operable in a plurality of contexts, said system comprising:
-
a hardware processor kernel comprising a plurality of context control registers, each of said context control registers being associated with a corresponding one context of said plurality of contexts for controlling execution of a context; a plurality of sets of hardware registers, each set of said plurality of sets of hardware registers corresponding to one context of said plurality of contexts and being automatically operable with said plurality of context control registers to prevent priority inversion.
-
-
13. A processor system having an operating system operable in a plurality of contexts, said system comprising:
-
a hardware processor kernel comprising a plurality of context control registers, each of said context control registers being associated with a corresponding one context of said plurality of contexts for controlling execution of a context; a plurality of sets of hardware registers, each set of said plurality of sets of hardware registers corresponding to one context of said plurality of contexts; each of said sets of hardware registers comprising one register having a field that is conditionally writeable; each said one register being operable such that a second context of said plurality of contexts will attempt to write a value to said field to seize control from a first context; each said one register being further operable such that if a write of a predetermined value to said field is successful said second context takes a claim and may proceed to execute; each said one register further operable such that if said write of said predetermined value to said field is not successful said second context will pend until said first context completes execution.
-
Specification