Semiconductor Memory and Method of Manufacturing the Same

• US 20080073635A1
• Filed: 09/20/2007
• Published: 03/27/2008
• Est. Priority Date: 09/21/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio, Kiyotoshi, Masahiro, Arai, Fumitaka, Yamamoto, Akihito, Shirota, Riichiro
• Granted Patent: US 8,008,732 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/021 : Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/028 : by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/801 : Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8413 : adapted for resistive heating
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Claims

1. A semiconductor memory comprising:

a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate;

a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate;

a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate; and

wherein the layers are patterned in self-alignment with each other,

intersections of the active areas and the first gate electrode form a plurality of memory cells, and

the plurality of memory cells in an intersecting plane share the first gate electrode.

2. The memory according to claim 1, wherein the first and second gate electrodes are formed by one layer.

3. The memory according to claim 1, wherein the first and second gate electrodes are connected to interconnections and driven independently of each other.

4. The memory according to claim 1, wherein the second gate electrode is formed parallel to the active areas, and shared by the plurality of memory cells in a plane parallel to the active areas and perpendicular to the substrate.

5. The memory according to claim 1, wherein a transistor of each of the memory cells is a transistor of depletion type.

6. The memory according to claim 1, wherein the active areas are made of one of single-crystal silicon and polysilicon.

7. The memory according to claim 1, further comprising layer selection gate transistors to select each layer to which a group of active areas, among other active areas, in a plane parallel to the substrate belongs.

8. The memory according to claim 1, wherein the active areas are formed in a recess dug down from a surface of the substrate.

9. The memory according to claim 1, wherein a memory element of the semiconductor memory is a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) element.

10. The memory according to claim 1, wherein

a memory element of the semiconductor memory is a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) element, and

a shape of a sidewall of each of the active areas has a curvature outward.

11. The memory according to claim 1, wherein the semiconductor memory is one of a PRAM (Phase Change RAM) and an RRAM (Resistive RAM).

12. A semiconductor memory manufacturing method comprising:

depositing a plurality of layers on a substrate;

forming a plurality of stripe-like active areas by processing the layers in self-alignment with each other; and

forming a plurality of gate electrodes intersecting the active areas in a longitudinal direction thereof,

wherein each of the active areas uses, as a channel region, at least one of two side surfaces perpendicular to the substrate,

intersections of the active areas and the gate electrodes form memory cells, and

a plurality of memory cells in an intersecting plane share the gate electrode.

13. The method according to claim 12, wherein

the layers are formed by alternately stacking an insulating film and one of an epitaxial silicon film and a polysilicon film on the substrate, and

the layers are simultaneously processed into stripes.

14. The method according to claim 12, in which the layers have a stacked structure in which an epitaxial silicon germanium film and an epitaxial silicon film are alternately stacked on the substrate, and

which further comprises:

forming gaps by removing the epitaxial silicon germanium film by selective wet etching; and

forming insulating films in the gaps.

15. The method according to claim 12, wherein the forming the gate electrodes comprises:

filling conductor films in gaps between the stripe-like active areas; and

Patterning the conductor films by reactive ion etching.

16. The method according to claim 12, wherein the forming the gate electrodes comprises:

filling insulator films in first gaps between the stripe-like active areas;

forming second gaps as templates of the gate electrodes;

filling memory dielectric layers and conductor films in the second gaps; and

processing the memory dielectric layers and the conductor films by CMP.

17. The method according to claim 12, which further comprises forming contact plugs connecting to the active areas, and

in which the contact plugs each extend over two adjacent active areas, and are in zigzag alignment with each other by one active area at two ends of each active area.

18. The method according to claim 12, further comprising:

filling insulating films between rows of the stripe-like active areas;

forming gaps as templates of the gate electrodes in the insulating films;

forming recesses in sidewalls of the active areas by using the insulating films as masks; and

forming diodes by filling, in the recesses, semiconductor films having a conductivity type different from the active areas or by forming, on surfaces of the recesses, semiconductor layers having a conductivity type different from the active areas by gas phase doping.

19. The method according to claim 12, further comprising:

filling insulating films between rows of the stripe-like active areas;

forming gaps as templates of the gate electrodes in the insulating films;

forming, in sidewalls of the active areas, recessed diodes having a conductivity type different from the active areas by using the insulating films as masks; and

filling a conductive film in a space of each recessed diode,

wherein the semiconductor memory is one of a PRAM and an RRAM.

20. The method according to claim 12, in which the semiconductor memory is an RRAM, and

which further comprises:

filling a first electrode film in the space of each recessed diode; and

forming memory dielectric layers and second electrode films between the rows of the active areas.