III-V Hemt Devices

• US 20080073652A1
• Filed: 06/22/2005
• Published: 03/27/2008
• Est. Priority Date: 07/20/2004
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Nakano, Yoshitaka, Kachi, Tetsu, Ueda, Hiroyuki, Sugimoto, Masahiro, Uesugi, Tsutomu, Soejima, Narumasa
• Granted Patent: US 7,777,252 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

The semiconductor device has a stacked structure in which a p-GaN layer 32, an SI-GaN layer 62, and an AlGaN layer 34 are stacked, and has a gate electrode 44 that is formed at a top surface side of the AlGaN layer 34. A band gap of the AlGaN layer 34 is wider than a band gap of the p-GaN layer 32 and the SI-GaN layer 62. Moreover, impurity concentration of the SI-GaN layer 62 is less than 1×10¹⁷ cm⁻³. The semiconductor devices comprising III-V semiconductors that have a stable normally-off operation are realized.

Claims

1. A transistor comprising:

a first layer;

a middle layer stacked on a top surface of the first layer;

a second layer stacked on a top surface of the middle layer; and

an electrode formed at a top surface side of the second layer;

wherein the first layer comprises a first III-V nitride semiconductor having a first conductivity type,

the middle layer comprises the first III-V nitride semiconductor having an impurity concentration of less than 1×

10¹⁷ cm<sup>−

3</sup> and the thickness of the middle layer is approximately 5 nm to 15 nm,

the second layer comprises a second III-V nitride semiconductor having a second conductivity type or a substantially semi-insulating type, and

a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor.

2. A transistor as defined in claim 1,

wherein the middle layer is formed within a potential well that is formed defined by the first layer and the second layer.

3. A transistor comprising:

a first layer;

a second layer stacked on a top surface of the first layer; and

an electrode formed at a top surface side of the second layer;

wherein the first layer comprises a first III-V nitride semiconductor,

the second layer comprises a second III-V nitride semiconductor,

a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor, and

the first layer has an N face at a junction between the first layer and the second layer, and

the second layer has a III group face at the junction.

4. A transistor as defined in claim 3,

wherein an electric field generated by piezoelectric polarization in the second layer has a direction opposite to a direction of an electric field generated by spontaneous polarization in the second layer.

5. A transistor as defined in claim 3,

wherein a direction of an electric field generated by polarization in the second layer extends from the junction between the first layer and the second layer.

6. A transistor as defined in claim 3,

wherein the first layer has a first conductivity type or a substantially semi-insulating type, and

the second layer has a second conductivity type.

7. A transistor comprising:

a first layer;

a second layer stacked on a top surface of the first layer;

a surface layer stacked on a top surface of the second layer; and

an electrode formed at a top surface side of the surface layer;

wherein the first layer comprises a first III-V nitride semiconductor,

the second layer comprises a second III-V nitride semiconductor having a second conductivity type,

the surface layer comprises a III-V nitride semiconductor having a first conductivity type, and

a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor.

8. A transistor as defined in claim 7,

wherein the III-V nitride semiconductor in the surface layer is the second III-V nitride semiconductor.

9. A transistor comprising:

a first layer;

a plurality of units of layers, wherein each of the units of layers comprises a second layer and an upper layer stacked on a top surface of the second layer, and each of the units of layers is stacked on a top surface of a lower unit of layers; and

an electrode formed at a top surface side of the uppermost unit of layers;

wherein the first layer comprises a first III-V nitride semiconductor,

the second layer comprises a second III-V nitride semiconductor having a second conductivity type,

the upper layer comprises a III-V nitride semiconductor having a first conductivity type, and

a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor.

10. A transistor as defined in claim 9,

wherein the III-V nitride semiconductor in the upper layer is the second III-V nitride semiconductor.

11. A method for manufacturing a transistor having a first layer, a middle layer stacked on a top surface of the first layer, a second layer stacked on a top surface of the middle layer, and an electrode formed at a top surface side of the second layer, the method comprising:

growing the middle layer on the top surface of the first layer by epitaxial growth under conditions wherein an impurity supply rate is controlled such that impurity concentration of the middle layer is maintained to be less than 1×

10¹⁷ cm<sup>−

3</sup> and the thickness of the middle layer is restricted from 5 nm to 15 nm,

growing the second layer on the top surface of the middle layer by epitaxial growth; and

forming the electrode at the top surface side of the second layer;

wherein the first layer comprises a first III-V nitride semiconductor having a first conductivity type,

the middle layer comprises the first III-V nitride semiconductor,

the second layer comprises a second III-V nitride semiconductor having a second conductivity type or a substantially semi-insulating type, and

a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V semiconductor.

12. A method for manufacturing a transistor defined in claim 11,

wherein the step of growing the middle layer is controlled such that the middle layer is formed within a potential well defined by the first layer and the second layer.

13. A method for manufacturing a transistor having a first layer, a second layer stacked on a top surface of the first layer, and an electrode formed at a top surface side of the second layer, the method comprising:

growing the second layer on the top surface of the first layer by epitaxial growth, wherein the top surface of the first layer has N face, and a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor; and

forming the electrode at the top surface side of the second layer.

14. A method for manufacturing a transistor defined in claim 13,

wherein the first layer has a first conductivity type or a substantially semi-insulating type, and

the second layer has a second conductivity type.

15. A method for manufacturing a transistor having a first layer, a second layer stacked on a top surface of the first layer, a surface layer stacked on a top surface of the second layer, and an electrode formed at a top surface side of the surface layer, the method comprising:

growing the second layer on the top surface of the first layer by epitaxial growth;

growing the surface layer on the top surface of the second layer by epitaxial growth;

forming the electrode at the top surface side of the surface layer;

wherein the first layer comprises a first III-V nitride semiconductor,

the second layer comprises a second III-V nitride semiconductor having a second conductivity type,

the surface layer comprises a III-V nitride semiconductor having a first conductivity type, and

a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor.

16. A method for manufacturing a transistor defined in claim 15,

wherein the III-V nitride semiconductor in the surface layer is the second III-V nitride semiconductor.

17. A method for manufacturing a transistor having a first layer, a plurality of units of layers, and an electrode formed at a top surface side of the uppermost unit of layers, wherein each of the units of layers comprises a second layer and an upper layer stacked on a top surface of the second layer, and each of the units of layers is stacked on a top surface of a lower unit of layers, the method comprising:

(a) growing the second layer on the top surface of the first layer by epitaxial growth;

(b) growing the upper layer on a top surface of the second layer by epitaxial growth;

(c) growing the second layer on a top surface of the upper layer by epitaxial growth;

(d) growing the upper layer on a top surface of the second layer by epitaxial growth;

(e) repeating steps (c) and (d) for a predetermined cycle; and

(f) forming the electrode at a top surface side of an uppermost upper layer;

wherein the first layer comprises a first III-V nitride semiconductor,

the second layer comprises a second III-V nitride semiconductor having a second conductivity type,

the upper layer comprises a III-V nitride semiconductor having a first conductivity type, and

a band gap of the second III-V nitride semiconductor is wider than a band gap of the first III-V nitride semiconductor.

18. A method for manufacturing a transistor defined in claim 17,

wherein the III-V nitride semiconductor in the upper layer is the second III-V nitride semiconductor.