Power MOSFET with recessed field plate

• US 20080073707A1
• Filed: 09/25/2007
• Published: 03/27/2008
• Est. Priority Date: 09/27/2006
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: Mohamed N. Darwish
• Inventors: Darwish, Mohamed N.
• Granted Patent: US 7,843,004 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased.

Claims

1. A MOSFET formed in a semiconductor die comprising:

a gate trench extending from a surface of the die, the gate trench comprising a gate electrode, the gate electrode being separated from the die by a first dielectric layer, the first dielectric layer comprising a first section at a bottom of the gate trench and a second section at a sidewall of the gate trench, the first section being thicker than the second section;

a first recessed field plate (RFP) trench extending from the surface of the die, the first RFP trench containing a first RFP electrode, the first RFP electrode being separated from the die by a second dielectric layer;

a second RFP trench extending from the surface of the die, the second RFP trench containing a second RFP electrode, the second RFP electrode being separated from the die by a third dielectric layer, the gate trench being located between the first and second RFP trenches;

a mesa of the die between the gate trench and the first RFP trench;

a source region of a first conductivity type in the mesa adjacent the surface of the die and a sidewall of the gate trench;

a body region of a second conductivity type opposite to the first conductivity type adjacent the sidewall of the gate trench and the source region; and

a drain-drift region of the first conductivity type adjacent the body region;

wherein the respective bottoms of the first and second RFP electrodes are located at a level deeper below the surface of the die than a bottom of the gate electrode and wherein a depth of each of the first and second RFP trenches is substantially equal to a depth of the gate trench.

2. The MOSFET of claim 1 wherein the depth of each of the first and second RFP trenches is within +/−

10% of the depth of the gate trench.

3. The MOSFET of claim 1 wherein the depth of each of the first and second RFP trenches is within +/−

5% of the depth of the gate trench.

4. The MOSFET of claim 1 wherein the first and second RFP electrodes are electrically connected to the source region.

5. The MOSFET of claim 4 comprising a source contact layer overlying a surface of the die, the source contact layer comprising a conductive material and being in contact with the first and second RFP electrodes and the source region.

6. The MOSFET of claim 1 wherein the gate trench is equidistant from the first and second RFP trenches.

7. The MOSFET of claim 1 wherein a doping concentration of the drain-drift region in an area between the first RFP trench and the gate trench is less than a doping concentration of the drain-drift region in an area below the gate trench.

8. The MOSFET of claim 1 wherein the first and second RFP electrodes comprise polysilicon doped with a dopant of the first conductivity type.

9. The MOSFET of claim 1 wherein the first and second RFP electrodes comprise polysilicon doped with a dopant of the second conductivity type.

10. The MOSFET of claim 1 wherein the source contact layer comprises a tungsten plug, the tungsten plug being in contact with the RFP electrode.

11. The MOSFET of claim 1 further comprising a voltage-clamping region of the second conductivity type extending from the surface of the die, a depth of the voltage-clamping region being at a level between a bottom of the body region and a bottom of the RFP trench.

12. A MOSFET formed in a semiconductor die comprising:

a gate trench extending from a surface of the die, the gate trench comprising a gate electrode, the gate electrode being separated from the die by a first dielectric layer, the first dielectric layer comprising a first section at a bottom of the gate trench and a second section at a sidewall of the gate trench, the first section being thicker than the second section;

a recessed field plate (RFP) trench extending from the surface of the die, the RFP trench containing an RFP electrode, the RFP electrode being separated from the die by a second dielectric layer, a bottom of the RFP electrode being located at a level deeper below the surface of the die than a bottom of the gate electrode, the RFP electrode being electrically isolated from the gate electrode;

a mesa of the die between the gate trench and the RFP trench;

a source region of a first conductivity type in the mesa adjacent the surface of the die, the source region extending across the mesa between a sidewall of the RFP trench and a sidewall of the gate trench;

a body region of a second conductivity type opposite to the first conductivity type in the mesa, the body region being adjacent the source region and extending across the mesa between the sidewall of the RFP trench and the sidewall of the gate trench; and

a drain-drift region of the first conductivity type adjacent the body region.

13. The MOSFET of claim 12 wherein the body region comprises a body contact region adjacent the sidewall of the RFP trench, the body contact region being doped with a dopant of the second conductivity type and having a doping concentration greater than a doping concentration of a remaining portion of the body region, the MOSFET further comprising a source contact layer, the source contact layer comprising a conductive material, a top surface of the RFP electrode being recessed to a level below the surface of the die such that the source contact layer is in contact with the source region and the body contact region.

14. The MOSFET of claim 13 wherein the source contact layer comprises a tungsten plug, the tungsten plug being in contact with the body contact region.

15. The MOSFET of claim 13 wherein the body contact region extends to a level deeper below the surface of the die than a bottom of the remaining portion of the body region.

16. The MOSFET of claim 12 wherein a depth of the RFP trench is substantially equal to a depth of the gate trench.

17. The MOSFET of claim 12 comprising:

a second RFP trench extending from the surface of the die, the second RFP trench containing a second RFP electrode, the second RFP electrode being separated from the die by a third dielectric layer, a bottom of the second RFP electrode being located at a level deeper below the surface of the die than a bottom of the gate electrode;

a second mesa of the die between the gate trench and the second RFP trench;

a second source region of the first conductivity type in the second mesa adjacent the surface of the die, the second source region extending across the second mesa between a sidewall of the second RFP trench and a second sidewall of the gate trench;

a second body region of the second conductivity type in the mesa, the second body region being adjacent the second source region and extending across the second mesa between the sidewall of the RFP trench and the second sidewall of the gate trench.

18. The MOSFET of claim 17 wherein a depth of each of the RFP trench and the second RFP trench is substantially equal to a depth of the gate trench.

19. A MOSFET formed in a semiconductor die comprising:

a gate trench extending from a surface of the die, the gate trench comprising a gate electrode, the gate electrode being separated from the die by a first dielectric layer, the first dielectric layer comprising a first section at a bottom of the gate trench and a second section at a sidewall of the gate trench, the first section being thicker than the second section;

a first recessed field plate (RFP) trench extending from the surface of the die, the first RFP trench containing a first RFP electrode, the first RFP electrode being separated from the die by a second dielectric layer;

a second RFP trench extending from the surface of the die, the second RFP trench containing a second RFP electrode, the second RFP electrode being separated from the die by a third dielectric layer, the gate trench being located between the first and second RFP trenches;

a mesa of the die between the gate trench and the first RFP trench;

a source region of a first conductivity type in the mesa adjacent the surface of the die and a sidewall of the gate trench;

a body region of a second conductivity type opposite to the first conductivity type adjacent the sidewall of the gate trench and the source region; and

a drain-drift region of the first conductivity type adjacent the body region;

wherein the respective bottoms of the first and second RFP electrodes are located at a level deeper below the surface of the die than a bottom of the gate electrode and wherein a depth of each of the first and second RFP trenches is in a range of more than 50% and less than 80% of a depth of the gate trench.

20. A method of fabricating a MOSFET comprising:

providing a semiconductor die;

etching the die so as to form a gate trench and a recessed field plate (RFP) trench, the gate trench and the RFP trench extending from a surface of the die and being of substantially equal depth;

forming an insulating layer at a bottom of the gate trench;

forming a gate dielectric layer on a sidewall of the gate trench above the insulating layer;

forming a second dielectric layer along the walls of the RFP trench;

introducing conductive material into the gate trench to form a gate electrode;

introducing conductive material into the RFP trench to form an RFP electrode;

implanting dopant of a first conductivity type form a body region in the mesa adjacent the sidewall of the gate trench;

implanting dopant of a second conductivity type opposite to the first conductivity type to form a source region in the mesa adjacent the surface of the die; and

depositing a source contact layer on the surface of the die in contact with the source region, the source contact layer comprising a conductive material.

21. The method of claim 20 comprising forming a third dielectric layer above the gate electrode such that the source contact layer is not in contact with the gate electrode

22. The method of claim 21 wherein depositing a source contact layer causes the source contact layer to be in contact with the RFP electrode.

23. The method of claim 22 comprising implanting dopant of a first conductivity type to form a body contact region adjacent the body region and a sidewall of the RFP trench, the method further comprising etching the RFP electrode into the RFP trench such that depositing a source contact layer causes the source contact layer to be in contact with the body contact region.

24. The method of claim 20 comprising:

forming a mask layer on the surface of the die;

patterning the mask layer to form three openings, a first opening being located where the RFP trench is to be formed, a second opening being located where the gate trench is to be located, and a third opening being located where a second RFP trench is to be located, the second opening being located between and equidistant from the first and third openings; and

wherein etching the die comprises etching the die through the first, second and third openings to form the RFP trench, the gate trench and the second RFP trench, respectively, the gate trench being located between and equidistant from the RFP and second RFP trenches.

25. The method of claim 24 wherein etching the die causes the gate trench and the RFP trenches to have respective depths within a tolerance of +/−

10%.