Semiconductor device and method of manufacturing the same

• US 20080073709A1
• Filed: 09/19/2007
• Published: 03/27/2008
• Est. Priority Date: 09/22/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Fujimoto, Hiroyuki, Ueda, Yasuhiko
• Granted Patent: US 7,696,569 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor device in which the reliability of a gate dielectric film is high and a channel length is sufficiently secured and a method of manufacturing the same are provided. The semiconductor device comprises a trench gate transistor. The trench gate transistor comprises: a trench provided in a semiconductor substrate; a gate electrode formed in the trench through a gate dielectric film; and a diffusion layer formed in the vicinity of the trench. The trench comprises: an opening portion provided in a surface of the semiconductor substrate; a recess curved surface portion whose cross-sectional contour is a substantially circular arc shape; and a connection curved surface portion connecting the recess curved surface portion and the opening portion. The connection curved surface portion and the recess curved surface portion are integrated in a continuous curved surface without interposing a ridge line portion therebetween.

Claims

1. A semiconductor device comprising a trench gate transistor which comprises:

a trench provided in a semiconductor substrate;

a gate electrode formed in the trench through a gate dielectric film; and

a diffusion layer formed in the vicinity of the trench,

wherein the trench comprises;

an opening portion provided in a surface of the semiconductor substrate;

a recess curved surface portion whose cross-sectional contour is a substantially circular arc shape; and

a connection curved surface portion connecting the recess curved surface portion and the opening portion, and

the connection curved surface portion and the recess curved surface portion are integrated in a continuous curved surface without interposing a ridge line portion between the connection curved surface portion and the recess curved surface portion.

2. The semiconductor device as recited in claim 1, wherein the width of an opening of the connection curved surface portion is a minimum width of the trench.

5. The semiconductor device as recited in claim 1, wherein the semiconductor device is a dynamic random access memory using the trench gate transistor as a transfer gate transistor of a memory cell.

3. A semiconductor device comprising a trench gate transistor which comprises:

a trench provided in a semiconductor substrate;

a gate electrode formed in the trench through a gate dielectric film; and

a diffusion layer formed in the vicinity of the trench,

wherein a cross-sectional contour of the trench is substantially U-shaped, a width of an opening portion of the trench is smaller than the width of a bottom portion of the trench, and a surface extending from the opening portion to the bottom portion has a curved surface.

4. The semiconductor device as recited in claim 3, wherein no ridge line portion is present in the surface extending from the opening portion to the bottom portion.

6. The semiconductor device as recited in claim 3, wherein the semiconductor device is a dynamic random access memory using the trench gate transistor as a transfer gate transistor of a memory cell.

7. A method of manufacturing a semiconductor device having a trench gate transistor, comprising:

forming a trench in a semiconductor substrate; and

forming a gate dielectric film and a gate electrode in the trench,

wherein the step of forming the trench in the semiconductor substrate comprises;

forming a first recess portion in the semiconductor substrate;

after forming an oxide film on an inner surface of the first recess portion, removing the oxide film located at a bottom surface of the first recess portion;

forming a second recess portion connected to the first recess portion by etching the bottom surface of the first recess portion using the oxide film remaining on a side surface of the first recess portion as a mask;

performing hydrogen anneal to make a cross-sectional contour of the second recess portion a substantially circular arc shape;

performing sacrifice oxidation; and

removing the oxide film.

8. The method as recited in claim 7, wherein the sacrifice oxidation is performed in an atmosphere including organic halide gas.

9. The method as recited in claim 7, wherein the oxide film to be formed in the first recess portion is formed in a thermal oxidation method.

10. The method as recited in claim 7, wherein the bottom surface of the first recess portion is etched by simultaneously performing anisotropic etching and isotropic etching.

11. The method as recited in claim 9, wherein the thermal oxidation method is thermal oxidation in an oxidizing atmosphere to which organic halide gas is added.