Semiconductor device with a vertical MOSFET and method for manufacturing the same

• US 20080073710A1
• Filed: 09/20/2007
• Published: 03/27/2008
• Est. Priority Date: 09/26/2006
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yamamoto, Hideo
• Application Number:
  US11/902,243
• Publication Number:
  US 20080073710A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The size of a gate contact region is decreased by connecting a gate connection electrode embedded in a trench and a gate wiring formed over the gate connection electrode, without forming another conductive film different from the gate connection electrode or the gate wiring. The semiconductor body includes an active cell region and a gate contact region. The active cell region includes a vertical MOSFET with a gate electrode disposed in a first trench. The gate contact region includes the gate connection electrode disposed in a second trench and formed of a same conductive material with the gate electrode. The gate connection electrode includes an embedded part formed in the second trench and an extended part extended therefrom and formed outside the second trench. An interlayer insulation film formed on the gate connection electrode and having a via hole exposing at least a portion of the embedded part of the gate connection electrode.

Claims

1. A semiconductor device, comprising:

a semiconductor body including an active cell region and a gate contact region;

a base region formed in said semiconductor body in said active cell region;

a first trench formed in said base region in said active cell region;

a gate electrode formed in said first trench;

a source region formed in said base region in said active cell region;

a source wiring connected to said source region and said base region in said active region;

a second trench formed in said semiconductor body in said gate contact region;

a gate connection electrode formed in said second trench, said gate connection electrode including an embedded part that is formed in said second trench and an extended part that is extended from said embedded part and is formed outside of said second trench,

an interlayer insulation film formed on said gate connection electrode and having a via hole over lapping with said embedded part of said gate connection electrode; and

a gate wiring connected to said gate connection electrode through said via hole.

2. The semiconductor device according to claim 1, wherein said via hole further exposes a portion of said extended part of said gate connection electrode.

3. The semiconductor device according to claim 1, further comprising an embedded insulating film,

wherein said gate electrode is partially filled in said first trench in said active cell region, and

wherein a remaining portion of said first trench in said active cell region is filled with said embedded insulating film is formed on said gate electrode.

4. The semiconductor device according to claim 3, wherein said embedded insulating film is further formed on said embedded part of said gate connection electrode.

5. The semiconductor device according to claim 1, wherein said source electrode and said gate wiring are formed of a same conductive material.

6. A process for manufacturing a semiconductor device, comprising:

forming a first trench in an active cell region in a semiconductor body and a second trench in a gate contact region in said semiconductor body, respectively;

forming a gate insulating film and a conductive material in each of said first trench and said second trench;

patterning said conductive material and forming a gate electrode in said first trench and a gate connection electrode in said second trench, said gate connection electrode including an embedded part that is formed in said second trench and an extended part that is extended from said embedded part and is formed outside of said second trench;

forming an interlayer insulation film on said gate connection electrode;

forming a via hole in said interlayer insulation film so as to overlap with said embedded part of said gate connection electrode; and

forming a gate wiring connected to said gate connection electrode through said via hole.

7. The process for manufacturing a semiconductor device according to claim 6, wherein said via hole further exposes a portion of said extended part of said gate connection electrode.

8. The process for manufacturing a semiconductor device according to claim 6, further comprising:

forming an embedded insulating film on said gate electrode in said first trench;

forming a base region in said active element region in said semiconductor body;

forming a source region in said base region; and

forming a source electrode connected to said source region and said base region in said active element region,

wherein said gate electrode is partially filled in said first trench, said embedded insulating film is formed on said gate electrode in the remaining portion of said first trench, and

wherein said source electrode is formed on a substantially coplanar surface formed by the upper surface of each of said base region, said source region, and said embedded insulating film.

9. The process for manufacturing a semiconductor device according to claim 8, wherein said forming said embedded insulating film is further forming another embedded film on said embedded part of said gate connection electrode, and said gate wiring contacts to both of said gate connection electrode and said another embedded insulating film.

10. The semiconductor device according to claim 8, wherein the source electrode and the gate wiring are formed simultaneously.