High withstand voltage transistor and manufacturing method thereof, and semiconductor device adopting high withstand voltage transistor

• US 20080073731A1
• Filed: 09/24/2007
• Published: 03/27/2008
• Est. Priority Date: 09/26/2006
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Hayashi, Keiji
• Granted Patent: US 7,843,020 B2
• Time in Patent Office: Days
• US Class Current: 257/409
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode and another side of the gate electrode, and which are a predetermined distance away from the gate electrode; first electric field relaxation layers one of which is formed on a wall of the trench on the side of the source and another one of which is formed on a wall of the trench on the side of the drain; and second electric field relaxation layers one of which is formed between the source and the gate electrode, and another one of which is formed between the drain and the gate electrode.

Claims

1. A high withstand voltage transistor, comprising:

a gate electrode provided in a first trench formed on a first conductive semiconductor substrate;

a source and a drain one of which is formed on one side of the gate electrode, and another one of which is formed on another side of the gate electrode, the source and the drain being apart from the gate electrode by a predetermined distance;

first electric field relaxation layers one of which is formed on a wall of the trench on the side of the source and another one of which is formed on a wall of the trench on the side of the drain;

second electric field relaxation layers one of which is formed between the source and the gate electrode, and is extended so as to surround the source, and another one of which is formed between the drain and the gate electrode, and is extended so as to surround the drain, wherein

a withstand voltage of a drain/source diffusion layer is 1 to 3V lower than that of the transistor.

2. The high withstand voltage transistor as set forth in claim 1, wherein:

a substrate impurity concentration on a surface of the semiconductor substrate is higher than a substrate impurity concentration in each of the first electric field relaxation layers.

3. The high withstand voltage transistor as set forth in claim 1, wherein:

a substrate impurity concentration of the trench bottom surface is lower than a substrate impurity concentration in each of the first electric field relaxation layers.

4. The high withstand voltage transistor as set forth in claim 1, wherein:

a substrate impurity concentration in a portion below a bottom surface of the trench is higher than a substrate impurity concentration on the bottom surface.

12. A semiconductor device, comprising:

the high withstand voltage transistor as set forth in claim 1;

and

an output terminal connected to the high withstand voltage transistor.

5. A method of manufacturing a high withstand voltage transistor, comprising the steps of:

(I) forming a first trench on a semiconductor substrate, and burying a CVD oxidized film;

(II) forming a first photoresist having an opening which is wider than the width of the first trench by an intended amount;

(III) implanting a first ion of a second conduction type, using the first photoresist as a mask; and

(IV) forming first electric field relaxation layers along walls of the first trench.

6. The method as set forth in claim 5, further comprising the steps of:

(V) forming a second trench by removing the CVD oxidized film in the first trench in which the first electric field relaxation layers are formed; and

(VI) forming a gate oxidized film on bottom and side surfaces of the second trench, and then forming a gate electrode in the second trench.

7. The method as set forth in claim 6, further comprising the steps of:

(VII) forming an insulation film having an intended width for covering the gate electrode;

(VIII) implanting a second ion of a second conduction type while using the insulation film as a mask, so as to form a source on one side of the insulation film and a drain on another side of the insulation film; and

(IX) (i) forming second electric field relaxation layers by implanting a third ion of a second conduction type so that one of the second electric field relaxation layers is below the insulation film and is extended so as to surround the source and, and another one of the second electric field relaxation layers is below the insulation film and is extended so as to surround the drain; and

(ii) electrically connecting the second electric field relaxation layers with the first electric field relaxation layers.

8. The method as set forth in claim 5, wherein:

the first ion is implanted into a position which is shallower than the bottom surface of the first trench.

9. The method as set forth in claim 7, wherein:

the third ion is implanted into a position which is shallower than a position where the first ion is implanted, but deeper than a position where the second ion is implanted.

10. The method as set forth in claim 7, wherein:

a drain/source junction withstand voltage is set by;

(i) a substrate impurity concentration on a surface of the semiconductor substrate; and

(ii) implantation of the third ion.

11. The method as set forth in claim 5, wherein:

a withstand voltage of the transistor is set by;

(i) a substrate impurity concentration on the surface of the semiconductor substrate;

(ii) a substrate impurity concentration on the bottom surface of the trench; and

(iii) implantation of the first ion.