High-voltage MOS device improvement by forming implantation regions

• US 20080073745A1
• Filed: 09/25/2006
• Published: 03/27/2008
• Est. Priority Date: 09/25/2006
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ho, David, Huang, Tsung-Yi, Jong, Yu-Chang, Tang, Chien-Shao, Wang, Zhe-Yi
• Application Number:
  US11/526,419
• Publication Number:
  US 20080073745A1
• Time in Patent Office: Days
• US Class Current: 257/500
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A high-voltage semiconductor structure includes a high-voltage well region overlying a substrate, an isolation region extending from a top surface of the high-voltage well region into the high-voltage well region, a low-voltage well region having at least a portion underlying and adjoining the isolation region wherein the low-voltage well region is inside of and of a same conductivity type as the high-voltage well region, a gate dielectric on the high-voltage well region, a gate electrode on the gate dielectric, and a source/drain region of the same conductivity type as the high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.

Claims

1. A high-voltage semiconductor structure comprising:

a substrate;

a first high-voltage well region of a first conductivity type overlying the substrate;

an isolation region extending from a top surface of the first high-voltage well region into the first high-voltage well region;

a low-voltage well region having at least a portion underlying and adjoining the isolation region, wherein the low-voltage well region is inside of and of a same conductivity type as the first high-voltage well region;

a gate dielectric on the first high-voltage well region;

a gate electrode on the gate dielectric; and

a source/drain region of the first conductivity type in the first high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.

2. The semiconductor structure of claim 1, wherein the first conductivity type is p-type.

3. The semiconductor structure of claim 1, wherein the first conductivity type is n-type.

4. The semiconductor structure of claim 1 further comprising an additional low-voltage well region overlying the substrate and outside the first high-voltage well region, wherein the additional low-voltage well region has a same depth as the low-voltage well region.

5. The semiconductor structure of claim 4 further comprising a low-voltage MOS device in the additional low-voltage well region.

6. The semiconductor structure of claim 1 further comprising:

a second high-voltage well region over the substrate, wherein the second high-voltage well region is of the first conductivity type; and

a third high-voltage well region of a second conductivity type opposite the first conductivity type between the first and the second high-voltage well regions, wherein the gate dielectric further extends on portions of the second and third high-voltage well regions.

7. The semiconductor structure of claim 1 further comprising a buried layer of the first conductivity type overlying the substrate and underlying the first high-voltage well region.

8. The semiconductor structure of claim 1, wherein the low-voltage well region is substantially within alignment lines of the isolation region.

9. The semiconductor structure of claim 1 further comprising an additional source/drain region on an opposite side of the gate dielectric than the source/drain region.

10. The semiconductor structure of claim 9 further comprising an additional isolation region separating the gate dielectric and the additional source/drain region, and an additional low-voltage region underlying and adjoining the additional isolation region.

11. A semiconductor structure comprising:

a substrate comprising a high-voltage (HV) region and a low-voltage (LV) region;

a first high-voltage well region in the HV region, wherein the first high-voltage well region is doped with an impurity of a first conductivity type;

a second high-voltage well region in the HV region and adjoining the first high-voltage well region, wherein the second high-voltage well region is doped with an impurity of a second conductivity type opposite the first conductivity type;

a gate dielectric on a portion of the first high-voltage well region and extending on at least a portion of the second high-voltage well region;

a gate electrode on the gate dielectric;

a source/drain region of the first conductivity type in the first high-voltage well region;

an isolation region extending from a top surface of the first high-voltage well region into the first high-voltage well region, wherein the gate dielectric and the source/drain region are spaced apart by the isolation region;

a first low-voltage well region extending from a bottom surface of the isolation region into the first high-voltage well region, wherein the first low-voltage well region is of the first conductivity type, and wherein the first low-voltage region has a depth smaller than a depth of the first high-voltage well region; and

a second low-voltage well region in the LV region, wherein the first and second low-voltage well regions have a substantially same depth.

12. The semiconductor structure of claim 11 further comprising a low-voltage MOS device in the second low-voltage well region.

13. The semiconductor structure of claim 11, wherein the first conductivity type is n-type and the second conductivity type is p-type.

14. The semiconductor structure of claim 11, wherein the first conductivity type is p-type and the second conductivity type is n-type.

15. The semiconductor structure of claim 11, wherein the isolation region is a shallow trench isolation region.

16. The semiconductor structure of claim 11, wherein the first low-voltage well region has a width of between about 25 percent and about 75 percent of a width of the isolation region.

17. The semiconductor structure of claim 11, wherein the first low-voltage well region has a concentration at least about one order greater than a concentration of each of the first and second high-voltage well regions.

18. The semiconductor structure of claim 11 further comprising a third high-voltage well region of the first conductivity type adjacent the second high-voltage well region, wherein the gate dielectric further extends on a portion of the third high-voltage well region.

19. A method for forming a semiconductor structure, the method comprising:

providing a substrate;

forming a first high-voltage well region of a first conductivity type overlying the substrate;

forming a low-voltage well region, wherein the low-voltage well region is inside of the first high-voltage well region and of a same conductivity type as the first high-voltage well region;

forming an isolation region in the first high-voltage well region, wherein the isolation region has at least a portion on the low-voltage well region;

forming a gate dielectric on the first high-voltage well region;

forming a gate electrode on the gate dielectric; and

forming a source/drain region of the first conductivity type in the first high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.

20. The method of claim 19 further comprising forming an additional low-voltage well region overlying the substrate and outside the first high-voltage well region, wherein the additional low-voltage well region and the low-voltage well region are simultaneously formed.

21. The method of claim 20 further comprising forming a low-voltage MOS device in the additional low-voltage well region.

22. The method of claim 19 further comprising:

forming a second high-voltage region over the substrate simultaneously with the formation of the first high-voltage well region; and

forming a third high-voltage well region of a second conductivity type opposite the first conductivity type between the first and the second high-voltage well regions, wherein the gate dielectric further extends on portions of the second and third high-voltage well regions.

23. The method of claim 19, wherein the step of forming the isolation region comprises forming a shallow trench isolation region.

24. The method of claim 19, wherein the step of forming the isolation region comprises forming a field oxide region.

25. The method of claim 19 further comprising forming an additional source/drain region on an opposite side of the gate dielectric than the source/drain region.

26. The method of claim 25 further comprising forming an additional isolation region separating the gate dielectric and the additional source/drain region, and an additional low-voltage region underlying and adjoining the additional isolation region.

27. A method for forming a semiconductor structure, the method comprising:

providing a substrate;

forming a first high-voltage well region, doped with an impurity of a first conductivity type, overlying the substrate;

forming a second high-voltage well region, doped with an impurity of a second conductivity type opposite the first conductivity type, overlying the substrate and adjoining the first high-voltage well region;

simultaneously forming a first low-voltage well region in the first high-voltage well region and a second low-voltage well region outside a high-voltage well region, wherein the first and the second low-voltage well regions are of the first conductivity type, and wherein the low-voltage region has a depth smaller than a depth of the first high-voltage well region;

forming an isolation region extending from a top surface of the first high-voltage well region into the first high-voltage well region, wherein the isolation region has at least a portion overlapping the low-voltage well region, and wherein the isolation region is shallower than the low-voltage well region;

forming a gate dielectric on the first and the second high-voltage well regions and a portion of the isolation region;

forming a gate electrode on the gate dielectric;

forming a drain region of the first conductivity type in the first high-voltage well region and adjacent the isolation region; and

forming a source region of the first conductivity type in a high-voltage well region and on an opposite side of the gate dielectric from the drain region.

28. The method of claim 27 further comprising forming a low-voltage MOS device in the second low-voltage well region.

29. The method of claim 27, wherein the steps of forming the first and the second high-voltage well regions comprise epitaxially growing a semiconductor layer over the substrate, and implanting the first and second high-voltage well regions.

30. The method of claim 27, wherein the steps of forming the first and second high-voltage well regions comprise directly implanting the substrate to form the first and second high-voltage well regions.

31. The method of claim 27 further comprising forming a third high-voltage well region of the first conductivity type adjacent the second high-voltage well region and opposite the first high-voltage well region, wherein the gate dielectric further extends on a portion of the third high-voltage well region.