Electromagnetic shielding using through-silicon vias

• US 20080073747A1
• Filed: 09/22/2006
• Published: 03/27/2008
• Est. Priority Date: 09/22/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, C.S., Lu, Szu Wei, Chao, Clinton, Karta, Tjandra Winata, Peng, Mark Shane
• Granted Patent: US 7,427,803 B2
• Time in Patent Office: Days
• US Class Current: 257/520
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate;

a first integrated circuit in the semiconductor substrate;

a second integrated circuit in the semiconductor substrate; and

an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.

2. The integrated circuit structure of claim 1, wherein the isolation structure comprises a row of through-silicon vias.

3. The integrated circuit structure of claim 1, wherein the isolation structure comprises one solid through-silicon via in a form of a metal strip.

4. The integrated circuit structure of claim 1, wherein the isolation structure encircles the first integrated circuit.

5. The integrated circuit structure of claim 4 further comprising an additional isolation structure encircling the second integrated circuit.

6. The integrated circuit structure of claim 1 further comprising a backside conductive layer on a backside of the semiconductor substrate and electrically connected to the isolation structure.

7. The integrated circuit structure of claim 1 further comprising a metal cap over the first circuit region and in a metallization layer, wherein the metal cap is electrically connected to the isolation structure.

8. The integrated circuit structure of claim 1, wherein the isolation structure is grounded.

9. The integrated circuit structure of claim 1, wherein the isolation structure has a length greater than about 2 times lengths of the first and the second integrated circuits.

10. An integrated circuit structure comprising:

a semiconductor substrate;

a first circuit region in the semiconductor substrate;

a second circuit region in the semiconductor substrate; and

an isolation structure extending from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate, wherein the isolation structure comprises at least a portion separating the first circuit region and the second circuit region, and wherein the isolation structure is substantially longer than each of the first and the second circuit regions.

11. The integrated circuit structure of claim 10, wherein the isolation structure encircles the first circuit region.

12. The integrated circuit structure of claim 11 further comprising a backside plate on a backside of the semiconductor substrate, wherein the backside plate is electrically connected to the isolation structure.

13. The integrated circuit structure of claim 12 further comprising a metal cap in a metallization layer and over the first circuit region, wherein the metal cap is electrically connected to the isolation structure, and wherein the isolation structure, the metal cap and the backside plate form a cage enclosing the first circuit region.

14. The integrated circuit structure of claim 10, wherein the isolation structure comprises a row of through-silicon vias interconnected by a backside conductive layer.

15. The integrated circuit structure of claim 10 further comprising an additional semiconductor substrate stacked on the semiconductor substrate, wherein the additional semiconductor substrate comprises an additional isolation structure electrically connected to the isolation structure.

16. An integrated circuit structure comprising:

a semiconductor substrate;

a circuit region in the semiconductor substrate; and

an isolation structure enclosing the circuit region, wherein the isolation structure comprises;

at least one through-silicon via extending from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate;

a backside plate on a bottom surface of the semiconductor substrate, wherein the backside plate is electrically connected to the at least one through-silicon via; and

a metal cap in a metallization layer and over the circuit region, wherein the metal cap is electrically connected to the at least one through-silicon via.

17. The integrated circuit structure of claim 16, wherein the isolation structure is grounded.

18. The integrated circuit structure of claim 16, wherein the isolation structure comprises a plurality of through-silicon vias.

19. The integrated circuit structure of claim 16, wherein the isolation structure comprises one solid through-silicon via forming a ring.

20. The integrated circuit structure of claim 16, wherein the metal cap is in a form selected from the group consisting essentially of a solid plate, parallel interconnected metal lines, and a metal line grid.