Apparatus and method for testing conductive bumps

• US 20080074130A1
• Filed: 09/27/2006
• Published: 03/27/2008
• Est. Priority Date: 09/27/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu-Ting, Kuo, Yian-Liang, Lin, Yu-Chang
• Granted Patent: US 7,439,751 B2
• Time in Patent Office: Days
• US Class Current: 324/755
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 31/2896 Testing of IC packages; Test features related to IC packages containers per se H01L23/02, encapsulations per se H01L23/28
• CPC Class Codes: G01R 31/70 Testing of connections between components and printed circuit boards G01R31/68 takes precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An apparatus and method for testing conductive bumps are provided. An exemplary embodiment of a bump testing unit comprises a support substrate with two probes protruding one surface thereof. A digital detecting device is embedded in the support substrate, comprising a first and second input terminals and an output terminal, wherein the input terminals electrically connects one of the probes.

Claims

1. A bump testing unit, comprising:

a support substrate with at least two probes protruding from one surface thereof; and

a digital testing device embedded in the support substrate, comprising a first and second input terminals and an output terminal, wherein the first input terminal is electrically connected to one of the probes;

wherein the digital testing device is a flip-flop.

2. The bump testing unit as claimed in claim 1, wherein the support substrate comprises ceramic, epoxy, resin, polyimide, FR₄ or polymer.

3. The bump testing unit as claimed in claim 1, wherein the probes comprise tungsten rhenium (WRe), tungsten, Beryllium-Copper (BeCu) or Peliney®

.

4. The bump testing unit as claimed in claim 1, wherein the probes are electrically isolated from each other by the support substrate.

5. The bump testing unit as claimed in claim 1, further comprising a first circuit formed in the support substrate to electrically connect a third input terminal of the digital testing device and the probe not connected with the first input terminal, for providing the digital testing device with a set signal or providing the probe not connected to the first input terminal with a test signal.

6. The bump testing unit as claimed in claim 5, further comprising a second circuit formed in the support substrate to electrical connecting the second input terminal of the digital testing device, for providing the digital testing device with a first input signal.

8. The bump testing unit as claimed in claim 1, further comprising a third circuit formed in the support substrate, being electrically connected to the first input terminal of the digital testing device and the probe electrically connected thereto, for providing the digital testing device with a second signal.

7. (canceled)

9. An apparatus for instantaneously testing a plurality of conductive bumps, comprising:

a support substrate formed with a plurality of probes protruding one surface thereof; and

a plurality of digital testing devices embedded in the support substrate, each comprising a first and second input terminals and an output terminal, wherein each of the first input terminals is electrically connected to one of the probes and the output terminal of a previous digital testing device is connected to the second input terminal of a following digital testing device.

10. The apparatus as claimed in claim 9, wherein the support substrate comprises ceramic, epoxy, resin, polyimide, FR4 or polymer.

11. The apparatus as claimed in claim 9, wherein the probes comprise tungsten rhenium (WRe), tungsten, Beryllium-Copper (BeCu) or Peliney®

.

12. The apparatus as claimed in claim 9, wherein the probes are electrically isolated from each other.

13. The apparatus as claimed in claim 9, further comprising a first circuit formed in the support substrate to respectively connect a third input terminal of each of the digital testing devices and electrically connect the probes not connected with the first input terminal, for providing a set signal with each of the digital testing devices or providing a test signal with each of the probes not connected with the first input terminal.

14. The apparatus as claimed in claim 13, further comprising a second circuit formed in the support substrate to electrically connect the second input terminal of each of the digital testing devices, for providing each of the digital testing devices with a first input signal.

15. The apparatus as claimed in claim 9, further comprising a third circuit formed in the support substrate, electrically connecting the first input terminal of each of the digital testing devices and the probe electrically connected thereto, for providing each of the digital testing devices a second input signal.

16. The apparatus as claimed in claim 9, wherein the digital testing devices are flip-flops.

17. A method for testing conductive bumps, comprising the steps of:

providing a substrate with a region having a plurality of bumps, wherein every two bumps are electrically connected by a conductive section embedded in the substrate, forming a plurality of bump sections;

providing the apparatus of claim 9, wherein each of the digital testing devices respectively opposes one of the bump sections, each having two probes corresponding thereto;

contacting the probes of the apparatus with the bumps to form a conductive pathway between one of the bump sections and each of the digital testing devices connected thereto by the probes forming a connection;

providing a test signal to each of the probes not connected with the first input terminal and passes each conductive pathway, thereby testing the bumps and providing each of the digital testing devices a first input signal and the first input signal is recorded a test data by each of the digital testing devices; and

providing a second input signal to each of the digital testing devices by the second circuit, thereby reading out the test data recorded by each of the digital testing devices and obtain a data sequence.

18. The method as claimed in claim 17, wherein the second input signal squeezes out the test data recorded in each of the digital testing devices to thereby obtain a data sequence.

19. The method as claimed in claim 18, wherein the test signal is provided at a relative high voltage level and the first input signal recorded as the test data by each of the digital testing devices shows a relative high voltage level while the conductive pathway formed between one of the bump sections and each of the digital test devices connected thereto is normal but shows a relative low voltage level while malfunction bumps are existed in the corresponding bump section.

20. The method as claimed in claim 17, wherein data sequence is obtained in FIFO (first-in-first-out) sequence.