Interconnection and input/output resources for programmable logic integrated circuit devices

• US 20080074143A1
• Filed: 07/30/2007
• Published: 03/27/2008
• Est. Priority Date: 03/04/1999
• Status: Active Grant

• Current Assignee: Andrew Leaver, Bruce Pedersen, David Mendel, James Schleicher, Jim Park, Michael Hutton, Peter Kazarian, Rakesh Patel, Sergey Shumarayev, Tony Ngai, Victor Maruri, Wei-Jen Huang
• Original Assignee: Andrew Leaver, Bruce Pedersen, David Mendel, James Schleicher, Jim Park, Michael Hutton, Peter Kazarian, Rakesh Patel, Sergey Shumarayev, Tony Ngai, Victor Maruri, Wei-Jen Huang
• Inventors: Kazarian, Peter, Schleicher, James, Pedersen, Bruce, Patel, Rakesh, Shumarayev, Sergey, Mendel, David, Huang, Wei-Jen, Leaver, Andrew, Hutton, Michael, Ngai, Tony, Park, Jim, Maruri, Victor
• Granted Patent: US 7,492,188 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Claims

1. A programmable logic integrated circuit device comprising:

at least one logic region arranged in a plurality of rows and columns; and

at least one input/output (I/O) cell located within the plurality of rows and columns wherein;

at least some of the I/O cells include I/O signal communication regions; and

each said I/O signal communication region is operable to receive an input signal from a different I/O signal communication region and provide at least one output signal to at least one of the I/O signal communication regions that comprises either a registered or an unregistered form of said input signal.