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TILE SUB-ARRAY AND RELATED CIRCUITS AND TECHNIQUES

  • US 20080074324A1
  • Filed: 09/21/2006
  • Published: 03/27/2008
  • Est. Priority Date: 09/21/2006
  • Status: Active Grant
First Claim
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1. A tile subarray comprising:

  • a lower multi-layer assembly (LMLA) having a first surface with a plurality of packageless T/R modules electrically coupled thereto;

    a first interconnect board disposed over the plurality of T/R modules;

    a circulator board, disposed over said interconnect board;

    a second interconnect board disposed over said circulator board; and

    an upper multi-layer assembly (UMLA) disposed over said second interconnect board.

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