Computing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on external graphics cards

• US 20080074431A1
• Filed: 09/18/2007
• Published: 03/27/2008
• Est. Priority Date: 11/19/2003
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Bakalash, Reuven, Leviathan, Yaniv
• Application Number:
  US11/901,715
• Publication Number:
  US 20080074431A1
• Time in Patent Office: Days
• US Class Current: 345/506
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing

Abstract

A computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on external graphics cards. The computing system includes CPU memory space for storing one or more graphics-based applications, one or more CPUs for executing the graphics-based applications, a bridge circuit operably connecting the CPU memory space and the one or more CPUs, and multiple external graphics cards supporting multiple GPUs and connected to the bridge circuit by way of a data communication interface. The computing system further includes a multi-mode parallel graphics rendering system (MMPRS) supporting multiple modes of parallel operation. The MMPGRS includes a plurality of graphic processing pipelines (GPPLs), implemented using the GPUs, and an automatic mode control module. During the run-time of the graphics-based application, the automatic mode control module automatically controls the mode of parallel operation of the MMPGRS, so that the GPUs are driven in a parallelized manner under the control of the automatic mode control module.

Claims

1. A computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on external graphics cards, said computing system comprising:

CPU memory space for storing one or more graphics-based applications and a graphics library for generating graphics commands and data (GCAD) during the execution of said one or more graphics-based applications;

one or more CPUs for executing said graphics-based applications;

a bridge circuit operably connecting said CPU memory space and said one or more CPUs;

multiple external graphics cards supporting multiple GPUs and being connected to said bridge circuit by way of a data communication interface; and

a multi-mode parallel graphics rendering system (MMPRS) supporting multiple modes of parallel operation selected from the group consisting of object division, image division, and time division, and wherein each mode of parallel operation includes at least three stages, namely, decomposition, distribution and recomposition; and

wherein said MMPGRS includes;

(i) a plurality of graphic processing pipelines (GPPLs), implemented using said GPUs, and supporting a parallel graphics rendering process that employs one or more of said object division, image division and/or time division modes of parallel operation in order to execute graphic commands, process graphics data, and render pixel-composited images containing graphics for display on a display device during the run-time of said graphics-based application, and said display device being connectable to one of said multiple external graphics cards; and

(ii) an automatic mode control module for automatically controlling the mode of parallel operation of said MMPGRS during the run-time of said graphics-based application, so that said GPUs are driven in a parallelized manner under the control of said automatic mode control module, during the run-time of said graphics-based application.

2. The computing system of claim 1, wherein said MMPGRS comprises:

(i) a decomposition module for supporting the decomposition stage of parallel operation;

(ii) a distribution module for supporting the distribution stage of parallel operation; and

(iii) a recomposition module for supporting the recomposition stage of parallel operation.

3. The computing system of claim 2, wherein during operation,

(i) said decomposition module divides the stream of graphic commands and data according to the required parallelization mode, operative at any instant in time;

(ii) said distribution module uses said bridge circuit to distribute graphic commands and data to said multiple GPUs on board the external graphics cards,

(iii) said recomposition module uses said bridge circuit to transfer composited pixel data between said recomposition module and said multiple GPUs during the recomposition stage, and

(iv) finally recomposited pixel data sets are displayed as graphical images on said display device.

4. The computing system of claim 2, wherein said automatic mode control module, said decomposition module, said distribution module and said recomposition module are each implemented as a software package in said CPU memory space.

5. The computing system of claim 1, wherein said automatic mode control module employs the profiling of scenes in said graphics-based application.

6. The computing system of claim 5, wherein said profiling of scenes in said graphics-based application, is carried out in real-time during run-time of said graphics-based application.

7. The computing system of claim 6, wherein said real-time profiling of scenes in said graphics-based application involves (i) collecting and analyzing performance data associated with said MMPGRS and said computing system, during application run-time, (ii) constructing scene profiles for the image frames associated with particular scenes in said particular graphics-based application, and (iii) maintaining said scene profiles in a application/scene profile database that is accessible to said automatic mode control module during run-time, so that during the run-time of said graphics-based application, said automatic mode control module can access and use said scene profiles maintained in said application/scene profile database and determine how to dynamically control the modes of parallel operation of said MMPGRS to optimize system performance.

8. The computing system of claim 6, wherein said automatic mode control module employs real-time detection of scene profile indices programmed within pre-profiled scenes of said graphics-based application;

wherein said pre-profiled scenes are analyzed prior to run-time, and indexed with said scene profile indices; and

wherein and mode control parameters (MCPs) corresponding to said scene profile indices, are stored within a application/scene profile database accessible to said automatic mode control module during application run-time.

9. The computing system of claim 8, wherein during run-time, said automatic mode control module automatically detects said scene profile indices and uses said detected said scene profile indices to access corresponding MCPs from said application/scene profile database so as to determine how to dynamically control the modes of parallel operation of said MMPGRS to optimize system performance.

10. The computing system of claim 1, wherein said automatic mode control module employs real-time detection of mode control commands (MCCs) programmed within pre-profiled scenes of said graphics-based application;

wherein said pre-profiled scenes are analyzed prior to run-time, and said MCCs are directly programmed within the individual image frames of each scene; and

wherein during run-time, said automatic mode control module automatically detects said MCCs along the graphics command and data stream, and uses said MCCs so as to determine how to dynamically control the modes of parallel operation of said MMPGRS to optimize system performance.

11. The computing system of claim 1, wherein said automatic mode control module employs a user interaction detection (UID) mechanism for real-time detection of the user'"'"'s interaction with said computing system.

12. The computing system of claim 11, wherein, in conjunction with said scene profiling, said automatic mode control module also uses said UID mechanism to determine how to dynamically control the modes of parallel operation of the MMPGRS to optimize system performance, at any instance in time during run-time of said graphics-based application.

13. The computing system of claim 1, wherein said bridge circuit is a North memory bridge disposed between said CPU memory space and said one or more CPUs.