Discharge protection circuit

• US 20080074813A1
• Filed: 09/26/2006
• Published: 03/27/2008
• Est. Priority Date: 09/26/2006
• Status: Abandoned Application

• Current Assignee: Aviad Wertheimer, Rushdy Saba
• Original Assignee: Aviad Wertheimer, Rushdy Saba
• Inventors: Saba, Rushdy, Wertheimer, Aviad
• Application Number:
  US11/527,923
• Publication Number:
  US 20080074813A1
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

In some embodiments, a discharge protection circuit having an operational mode and a protection mode is provided.

Claims

1. A chip, comprising:

a signal node, a high supply referenced node, and a low supply reference node;

a power clamp coupled between the high and low supply reference nodes; and

a first rectifier coupled between the signal node and the high supply reference node and a second rectifier coupled between the signal node and the low supply reference node, said first and second rectifiers to unidirectionally block the supply reference nodes from the signal node to provide a signal operating window.

2. The chip of claim 1, in which the high supply reference is a virtual high supply reference node, the chip comprising a transistor coupled between a voltage supply and said virtual high supply reference node to controllably provide a high supply voltage at the virtual high supply reference node when a link partner is actively coupled to the signal node.

3. The chip of claim 2, in which the transistor is a PMOS transistor.

4. The chip of claim 2, comprising a second transistor coupled between the virtual high supply reference node and the low supply reference node to discharge the virtual high supply reference node during a protected mode.

5. The chip of claim 4, in which the second transistor comprises an NMOS transistor.

6. The chip of claim 4, in which the protected mode is entered when a link partner is not actively coupled to the signal node.

7. The chip of claim 1, in which the power clamp comprises a transistor controllably coupled to

8. The chip of claim 7, in which the power clamp comprises a timer circuit formed from a resistor and a capacitor coupled between the high and low supply reference nodes.

9. An integrated circuit, comprising:

a signal node to be coupled to an external link partner; and

a discharge protection circuit coupled to the signal node to provide it with a signal operating window when the link partner is actively coupled to the signal node.

10. The integrated circuit of claim 9, comprising a link detection circuit coupled to the discharge protection circuit to control it to provide the signal operating window when detecting the link partner actively coupled to the signal node.

11. The integrated circuit of claim 9, in which the discharge protection circuit comprises a power clamp coupled between a virtual high supply reference node and a low supply reference node.

12. The integrated circuit of claim 11, in which the discharge protection circuit comprises a transistor coupled between a voltage supply and said virtual high supply reference node to controllably provide a high supply voltage at the virtual high supply reference node when the link partner is actively coupled to the signal node.

13. The integrated circuit of claim 12, in which the transistor is a PMOS transistor.

14. The integrated circuit of claim 12, comprising a second transistor coupled between the virtual high supply reference node and the low supply reference node to discharge the virtual high supply reference node during a protected mode.

15. The integrated circuit of claim 14, in which the second transistor comprises an NMOS

16. The integrated circuit of claim 14, in which the protected mode is entered when a link partner is not actively coupled to the signal node.

17. The integrated circuit of claim 11, in which the power clamp comprises a transistor controllably coupled to a timer circuit coupled between the virtual high and low supply reference nodes.

18. A system, comprising:

(a) a microprocessor chip;

(b) at least one memory chip coupled to the microprocessor chip; and

(c) a link interface chip to coupled a link partner to the microprocessor chip, the link interface chip comprising a signal node to be coupled to the link partner, and a discharge protection circuit coupled to the signal node to provide it with a signal operating window when the link partner is actively coupled to the signal node.

19. The system of claim 18, in which the link interface chip comprises a link detection circuit coupled to the discharge protection circuit to control it to provide the signal operating window when detecting the link partner actively coupled to the signal node.

21. The chip of claim 19, in which the detection circuit causes the discharge protection circuit to be substantially discharged during the protected mode.

20. A chip comprising:

a detection circuit to detect a cable connection; and

a discharge protection circuit coupled to the detection circuit, the discharge protection circuit to be in a protection mode while the cable is being connected and for a duration after it has been connected.