Methods and systems for protection from over-stress

• US 20080075142A1
• Filed: 09/22/2006
• Published: 03/27/2008
• Est. Priority Date: 09/22/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Notarantonio, Raymond Joseph, Beier, Robert Carl
• Granted Patent: US 7,607,828 B2
• Time in Patent Office: Days
• US Class Current: 374/163
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

One embodiment of the invention relates to a circuit for over-stress protection. The circuit includes a temperature rate sensor configured to monitor the temperature of a semiconductor device during a first state. The circuit is further configured to selectively switch the semiconductor device from the first state to a second state if the temperature increases at a rate that has a predetermined relationship with a temperature rate function. Other methods and systems are also disclosed.

Claims

1. A circuit, comprising:

a temperature rate sensor configured to monitor the temperature of a semiconductor device during a first state and selectively switch the semiconductor device from the first state to a second state if the temperature increases at a rate that has a predetermined relationship with a temperature rate function.

2. The circuit of claim 1, wherein the temperature rate sensor comprises:

a temperature sensor configured to provide the temperature of the semiconductor device;

a differentiator configured to provide a differentiated temperature by differentiating the temperature; and

a comparator configured to compare the differentiated temperature to a reference level, and to provide a comparator output value therefrom.

3. The circuit of claim 2, wherein the reference level is adjustable and is representative of the temperature rate function.

4. The circuit of claim 3, further comprising:

a logic circuit that is coupled to the output node of the comparator, wherein the logic circuit utilizes the comparator output value to provide a logic control signal to switch the semiconductor device from the first state to the second state.

5. The circuit of claim 1 wherein the semiconductor device comprises a MOSFET.

6. A circuit for protection from over-stress, comprising:

a temperature rate sensor configured to monitor a temperature of a semiconductor device and integrate the temperature during an integration period;

wherein the integration period relates to a time at which the rate of temperature increase has a pre-determined relationship with a temperature rate function.

7. The circuit of claim 6, wherein the circuit is configured to selectively turn off the semiconductor device if the integrated temperature is greater than an integrated temperature function.

8. The circuit of claim 6, wherein the temperature rate sensor comprises:

a temperature sensor configured to provide the temperature of the semiconductor device;

a differentiator configured to aid in designating the start of the integration period; and

an integrator configured to integrate the temperature during the integration period.

9. The circuit of claim 8 wherein the temperature rate sensor further comprises:

a comparator configured to compare the differentiated temperature to a reference level, and to provide a comparator output value therefrom; and

a time period circuit configured to receive the comparator output value and provide the integration period therefrom.

10. The circuit of claim 9 wherein the temperature rate sensor further comprises:

a second comparator configured to compare the integrated temperature to an integrator temperature function, and provide a second comparator output value therefrom;

wherein the second comparator output value can facilitate switching the semiconductor device from the first state to the second state.

11. The circuit of claim 6, further comprising:

an inductor configured to generate flyback energy when turned from an on-state to an off-state by the semiconductor device;

wherein the circuit is configured to provide a diagnostic fault flag if the flyback energy causes the rate of temperature increase to have the predetermined relationship with the temperature rate function.

12. A method for protecting a semiconductor device from over-stress, comprising:

monitoring the temperature of a semiconductor device during an on-state;

comparing a temperature rate associated with the monitored temperature to a temperature rate function to facilitate switching the semiconductor device from the on-state to an off-state.

13. The method of claim 12, further comprising:

integrating the temperature of the semiconductor device over a time window; and

comparing the integrated temperature to an integrated temperature function to facilitate switching the device from the on-state to the off-state.

14. The method of claim 13, wherein the integrating starts at a time related to when the monitored temperature favorably compares to the temperature rate function.

15. The method of claim 14, further comprising:

measuring the absolute temperature of the semiconductor device; and

switching the semiconductor device to an off-state if the absolute temperature exceeds a maximum temperature.

16. A method for protecting a semiconductor device from over-temperature, comprising:

monitoring a temperature change of the semiconductor device due to flyback energy associated with turning off an inductive load;

providing a diagnostic flag if the temperature change has a predetermined relationship with a temperature function.

17. The method of claim 16, further comprising:

driving the inductive load with the semiconductor device prior to turning off the inductive load.

18. The method of claim 17, further comprising:

turning off the semiconductor device to turn off the inductive load; and

wherein monitoring the temperature change of the semiconductor device is performed while the semiconductor device is in an off-state.

19. The method of claim 16, wherein the predetermined relationship is met if the temperature change is greater than or equal to the temperature function.

20. A circuit for protection from over-stress, comprising:

means for monitoring the temperature of a semiconductor device during an on-state and for comparing a temperature rate associated with the monitored temperature to a temperature rate function; and

circuitry to facilitate switching the semiconductor device from a first state to a second state if the temperature rate favorably compares to the temperature rate function.

21. The circuit of claim 20, further comprising:

means for integrating the temperature of the semiconductor device over a time window.

22. The circuit of claim 21, wherein the means for integrating the temperature comprises:

integration means for integrating the temperature of the semiconductor device; and

means for providing an enabling signal that is representative of the time window for which integration is carried out.

23. The circuit of claim 22, further comprising:

means for comparing the integrated temperature to a integrated temperature function to facilitate switching the device from the on-state to the off-state.

24. The method of claim 23, further comprising:

diagnostic circuitry for delivering a diagnostic signal from the circuit, wherein the diagnostic signal is indicative of an excessive temperature in the circuit.