Methods of Forming Fine Patterns In Integrated Circuits Using Atomic Layer Deposition

• US 20080076070A1
• Filed: 10/30/2006
• Published: 03/27/2008
• Est. Priority Date: 09/08/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Yool, Cho, Han-ku, Yeo, Gi-sung, Lee, Ji-young, Lee, Doo-youl, Koh, Cha-won
• Application Number:
  US11/554,324
• Publication Number:
  US 20080076070A1
• Time in Patent Office: Days
• US Class Current: 430/311
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00

Abstract

A fine pattern is formed in an integrated circuit substrate, by forming a sacrificial pattern on the integrated circuit substrate. The sacrificial pattern includes tops and side walls. Atomic layer deposition is then performed to atomic layer deposit a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof, and on the integrated circuit substrate therebetween. The mask material layer that was atomic layer deposited is then etched, to expose the top and the integrated circuit therebetween, such that a mask material pattern remains on the side walls. The sacrificial pattern is then removed, and the integrated circuit substrate is then etched through the mask material pattern that remains.

Claims

1. A method of forming a fine pattern in an integrated circuit substrate, the method comprising:

sequentially forming a first hard mask layer and a second hard mask layer on the integrated circuit substrate, the second hard mask layer having an etch selectivity with respect to the first hard mask layer;

forming a photoresist pattern on the second hard mask layer, the photoresist pattern having a first line width and a first pitch;

forming a mask material layer on the photoresist pattern and the second hard mask layer by atomic layer deposition, the mask material layer including a material harder than the second hard mask layer;

etching the mask material layer until the photoresist pattern is exposed in order to form a mask pattern on side walls of the photoresist pattern, the mask pattern having a second pitch that is less than the first pitch;

removing the photoresist pattern;

etching the second hard mask layer using the mask pattern to form a second hard mask pattern;

etching the first hard mask layer using the second hard mask pattern as a mask to form a first hard mask pattern; and

etching the integrated circuit substrate using the first hard mask pattern as a mask to form a fine pattern having same pitch as the second pitch.

2. The method of claim 1, further comprising forming an organic anti-reflective layer on the second hard mask layer prior to the forming of the photoresist pattern.

3. The method of claim 1, wherein the forming of the photoresist pattern comprises:

coating a photoresist layer on the second hard mask layer;

exposing and developing the photoresist layer to form the photoresist pattern with a second line width larger than the first line width; and

trimming the photoresist pattern to the first line width using O₂ plasma.

4. The method of claim 1, further comprising surface-treating the photoresist pattern to reduce a line width roughness of the photoresist pattern prior to the forming of the mask material layer.

5. The method of claim 1, wherein the first hard mask layer comprises a spin-on-carbon layer and/or a bottom photoresist layer, and the second hard mask layer comprises a silicon-containing layer.

6. The method of claim 1, wherein the first hard mask layer comprises an amorphous carbon layer, and the second hard mask layer comprises an oxide layer.

7. The method of claim 1, wherein the mask material layer comprises a nitride layer formed by atomic layer deposition in a temperature range from about 30°

C. to about 130°

C.

8. The method of claim 1, further comprising:

removing the mask pattern between the etching of the second hard mask layer and the etching of the first hard mask layer;

removing the second hard mask pattern between the etching of the first hard mask layer and the etching of the integrated circuit substrate; and

removing the first hard mask pattern after the etching of the integrated circuit substrate.

9. A method of forming a fine pattern in an integrated circuit substrate, the method comprising:

forming an insulating layer on the integrated circuit substrate;

sequentially forming a first hard mask layer and a second hard mask layer on the insulating layer, the second hard mask layer having an etch selectivity with respect to the first hard mask layer;

forming a first photoresist pattern on the second hard mask layer, the first photoresist pattern having a first line width and a first pitch;

forming a mask material layer on the first photoresist pattern and the second hard mask layer by atomic layer deposition, the mask material layer including a material harder than the second hard mask layer;

etching the mask material layer until the first photoresist pattern is exposed in order to form a mask pattern on side walls of the first photoresist pattern, the mask pattern having a second pitch that is less than the first pitch;

etching a portion of the second hard mask layer using the mask pattern;

forming a second photoresist pattern on the second hard mask layer, the second photoresist pattern partially exposing the etched portion of the second hard mask layer;

etching the partially exposed portion of the second hard mask layer using the second photoresist pattern until the first hard mask layer is exposed, so as to form a second hard mask pattern;

etching the first hard mask layer using the second hard mask pattern as a mask to form a first hard mask pattern; and

etching the insulating layer using the first hard mask pattern as a mask to form a contact hole.

10. The method of claim 9, further comprising removing the mask pattern between the etching of the portion of the second hard mask layer and the forming of the second photoresist pattern.

11. The method of claim 9, further comprising:

forming a first organic anti-reflective layer on the second hard mask layer prior to the forming of the first photoresist pattern; and

forming a second organic anti-reflective layer on the second hard mask layer prior to the forming of the second photoresist pattern.

12. The method of claim 9, wherein the forming of the first photoresist pattern comprises:

coating a photoresist layer on the second hard mask layer;

exposing and developing the photoresist layer to form the first photoresist pattern with a second line width larger than the first line width; and

trimming the first photoresist pattern to the first line width using O₂ plasma.

13. The method of claim 9, further comprising:

surface-treating the first photoresist pattern to reduce a line width roughness of the first photoresist pattern between the forming of the first photoresist pattern and the forming of the mask material layer; and

surface-treating the second photoresist pattern to reduce a line width roughness of the second photoresist pattern between the forming of the second photoresist pattern and the etching of the partially exposed portion of the second hard mask layer.

14. The method of claim 9, wherein the first hard mask layer comprises a spin-on-carbon layer and/or a bottom photoresist layer, and the second hard mask layer comprises a silicon-containing layer.

15. The method of claim 9, wherein the first hard mask layer comprises an amorphous carbon layer, and the second hard mask layer comprises an oxide layer.

16. The method of claim 9, wherein the mask material layer comprises a nitride layer formed by atomic layer deposition in a temperature range from about 30°

C. to about 130°

C.

17. The method of claim 9, further comprising:

removing the first photoresist pattern between the etching of the mask material and the etching of the portion of the second hard mask layer;

removing the second photoresist pattern between the etching of the partially exposed portion of the second hard mask layer and the etching of the first hard mask layer;

removing the second hard mask pattern between the etching of the first hard mask layer and the etching of the insulating layer; and

removing the first hard mask pattern after the etching of the insulating layer.

18. A method of forming a fine pattern in an integrated circuit substrate, the method comprising:

forming a sacrificial pattern on the integrated circuit substrate, the sacrificial pattern including tops and side walls;

atomic layer depositing a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof and on the integrated circuit substrate therebetween;

etching the mask material layer that was atomic layer deposited to expose the tops and the integrated circuit substrate therebetween, such that a mask material pattern remains on the side walls;

removing the sacrificial pattern; and

etching the integrated circuit substrate through the mask material pattern that remains.

19. The method of claim 18 wherein atomic layer depositing a mask material layer comprises atomic layer depositing a nitride layer in a temperature range from about 30°

C. to about 130°

C.

20. The method of claim 19 wherein forming a sacrificial pattern on the integrated circuit substrate comprises forming a sacrificial photoresist pattern on the integrated circuit substrate.