Method of forming a fine pattern

• US 20080076071A1
• Filed: 10/28/2006
• Published: 03/27/2008
• Est. Priority Date: 09/07/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dong-Seok, Kang, Chang-Jin, Min, Gyung-Jin, Chung, Seung-Pil, Lim, Seok-Hyun
• Application Number:
  US11/588,496
• Publication Number:
  US 20080076071A1
• Time in Patent Office: Days
• US Class Current: 430/311
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00

Abstract

First, second and third layers are formed on a substrate for forming a fine pattern. A first mask pattern having a first space is formed on the third layer. A third layer pattern having a second space exposing the second layer is formed. A first sacrificial layer is formed on the second layer having the third layer pattern. A fourth layer is formed on the first sacrificial layer. A double mask pattern including the first and second mask patterns is formed using the second mask pattern in the second space. A second sacrificial layer is formed on the first sacrificial layer. A sacrificial layer pattern having a third space is formed by removing the double mask pattern, the third layer pattern, and a portion of the first sacrificial layer. An insulation layer pattern is formed by removing a portion of the first and second layers.

Claims

1. A method of forming a fine pattern, the method comprising:

forming a first layer, a second layer and a third layer on a semiconductor substrate;

forming a first mask pattern having a first space on the third layer, wherein the first space is configured to partially expose the third layer;

forming a third layer pattern having a second space configured to partially expose -the second layer by removing a portion of the third layer exposed by the first space;

forming a first sacrificial layer on a top surface of the first mask pattern, a sidewall and a bottom of the second space, and the second layer, wherein the first sacrificial layer is configured to have a substantially uniform thickness;

forming a fourth layer on the first sacrificial layer, wherein the fourth layer is configured to form a second mask pattern;

forming a double mask pattern including the first mask pattern and the second mask pattern by partially removing the fourth layer to form the second mask pattern filled in the second space;

forming a second sacrificial layer on the first sacrificial layer having the double mask pattern, wherein the second sacrificial layer is configured to expose a top surface of the double mask pattern;

forming a sacrificial layer pattern having a third space by removing the double mask pattern, the third layer pattern, and a first portion of the first sacrificial layer disposed beneath the second mask pattern, wherein the third space partially exposes the second layer, and the sacrificial layer pattern includes a second portion of the first sacrificial layer and the second sacrificial layer; and

forming an insulation layer pattern by removing a third portion of the second layer and a fourth portion of the first layer, wherein the third portion of the second layer is exposed by the third space and the fourth portion of the first layer is disposed beneath the third portion.

2. The method of claim 1, wherein the first layer and the first and the second sacrificial layers have substantially the same etching ratio, and the second layer has an etching selectivity with respect to the first layer.

3. The method of claim 1, wherein the third layer has a thickness substantially the same as that of the first sacrificial layer.

4. The method of claim 3, wherein the third layer and the first sacrificial layer are formed by an atomic layer deposition (ALD) process.

5. The method of claim 1, wherein the first layer and the first and the second sacrificial layers include silicon oxide and the second layer includes polysilicon.

6. The method of claim 1, wherein the third layer includes at least one of silicon nitride and silicon oxide.

7. The method of claim 1, the first and the second mask patterns include polysilicon.

8. The method of claim 1, wherein forming the second sacrificial layer comprises:

forming a preliminary second sacrificial layer on the first sacrificial layer to cover the double mask pattern; and

removing the preliminary second sacrificial layer until the top surface of the double mask pattern is exposed.

9. A method of forming a fine pattern, the method comprising:

forming a first layer and a second layer on a semiconductor substrate;

forming a third layer on the second layer having a thickness smaller than those of the first and the second layers;

forming a first mask pattern having a first space on the third layer, wherein the first space is configured to partially expose the third layer;

forming a third layer pattern having a second space configured to partially expose the second layer by removing a portion of the third layer exposed by the first space;

forming a first sacrificial layer on a top surface of the first mask pattern, a sidewall and a bottom of the second space, and the second layer;

forming a fourth layer on the first sacrificial layer, wherein the fourth layer is configured to form a second mask pattern having an etching ratio substantially the same as that of the first mask pattern;

forming a double mask pattern including the first mask pattern and the second mask pattern by partially removing the fourth layer to form the second mask pattern filled in the second space;

forming a preliminary second sacrificial layer on the first sacrificial layer;

forming a second sacrificial layer by removing the preliminary second sacrificial layer until the top surface of the double mask pattern is exposed;

forming a sacrificial layer pattern having a third space by performing an etching process using an etching selectivity between the second sacrificial layer and the double mask pattern to remove the double mask pattern, the third layer pattern, and a first portion of the first sacrificial layer disposed beneath the second mask pattern, wherein the third space partially exposes the second layer, and the sacrificial layer pattern includes a second portion of the first sacrificial layer and the second sacrificial layer;

forming a preliminary insulation layer pattern having a fourth space by performing an etching process using an etching selectivity between the second layer and the sacrificial layer pattern to remove a third portion of the second layer exposed by the third space, wherein the fourth space partially exposes the first layer; and

forming an insulation layer pattern having a fifth space by performing an etching process using an etching selectivity between the preliminary insulation layer pattern and the first layer to remove a fourth portion of the first layer exposed by the fourth space, wherein the fifth space partially exposes the semiconductor substrate.

10. The method of claim 9, wherein the third layer and the first sacrificial layer have substantially the same thickness and are formed by an atomic layer deposition (ALD) process.

11. The method of claim 9, wherein the first layer and the first and the second sacrificial layers include silicon oxide, the second layer and the first and the second mask patterns include polysilicon, and the third layer includes at least one of silicon nitride and silicon oxide.

12. The method of claim 9, wherein the first layer is configured to have an etching selectivity with respect to the second layer.

13. The method of claim 9, wherein the third layer is configured to have an etching selectivity with respect to the second layer.

14. The method of claim 9, wherein the first sacrificial layer is configured to have an etching selectivity with respect to the first mask pattern and an etching ratio substantially the same as that of the first layer.

15. The method of claim 9, wherein the preliminary second sacrificial layer is configured to have an etching ratio substantially the same as that of the first sacrificial layer.