Circuit and method for controlling charge injection in radio frequency switches

• US 20080076371A1
• Filed: 07/26/2007
• Published: 03/27/2008
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Alexander Dribinsky, Christopher Brindle, Dylan Kelly, Tae Kim
• Inventors: Kim, Tae, Brindle, Christopher, Dribinsky, Alexander, Kelly, Dylan
• Application Number:
  US11/881,816
• Publication Number:
  US 20080076371A1
• Time in Patent Office: Days
• US Class Current: 455/208
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state
• CPC Class Codes: H03K 17/08 Modifications for protecting switching circuit against overcurrent or overvoltage
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/284 in field effect transistor switches
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/689 with galvanic isolation between the control circuit and the output circuit H03K17/78 takes precedence
• CPC Class Codes: H03K 2217/0009 AC switches, i.e. delivering AC power to a load

Abstract

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

Claims

1. A switch circuit, comprising:

a) a plurality of switching transistors coupled in series to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors, wherein injected charge is generated at resistively-isolated nodes between the switching transistors; and

b) a plurality of charge injection control elements operatively coupled to the switching transistors, and wherein the charge injection control elements receive the injected charge from the resistively-isolated nodes and convey the injected charge to at least one node of the switch circuit that is not resistively-isolated.

2. The switch circuit of claim 1, wherein each switching transistor has an associated and corresponding charge injection control element, and wherein a drain node of each switching transistor is coupled to a first node of its associated and corresponding charge injection control element, and wherein a source node of each switching transistor is coupled to a second node of its associated and corresponding charge injection control element, and wherein each charge injection control element conveys the injected charge between the drain node and the source node of its associated and corresponding switching transistor.

3. The switch circuit of claim 1, wherein each of the switching transistors comprises an accumulated charge control (ACC) transistor.

4. The switch circuit of claim 3, wherein the ACC transistor includes an accumulated charge sink (ACS) electrically coupled to convey accumulated charge from the ACS to a gate terminal of the ACC transistor when the ACC transistor operates in an accumulated charge regime.

5. The switch circuit of claim 4, wherein a diode selectively conveys accumulated charge from the ACS to the gate terminal of the ACC transistor when the ACC transistor operates in an accumulated charge regime.

6. The switch circuit of claim 2, wherein each charge injection control element comprises a charge injection control resistor.

7. The switch circuit of claim 6, further comprising a plurality of gate resistors each having a resistance Rg, wherein a gate of each switching transistor is connected to an associated and corresponding one of the plurality of gate resistors, and wherein the plurality of gate resistors is connected to a control line that conveys a control signal to the gate of each switching transistor, and wherein a resistance Rc of each charge injection control resistor is selected according to a formula 10×

Rg/N>

Rc>

Rg/10N, and wherein N comprises a number of switching transistors in the plurality of switching transistors.

8. The switch circuit of claim 2, wherein the charge injection control elements comprise switching circuits having an ON-state and an OFF-state, and wherein a control signal selectively switches the charge injection control elements from the ON-state to the OFF-state at a time subsequent to a time at which each switching transistor is switched from an ON-state to an OFF-state.

9. The switch circuit of claim 8, wherein the charge injection control elements comprise charge injection control transistors.

10. The switch circuit of claim 1, wherein the switch circuit comprises a radio frequency (RF) switch.

11. The switch circuit of claim 3, wherein the ACC transistor uses a pulse method for controlling accumulated charge.

12. The switch circuit of claim 1, wherein the plurality of switching transistors comprise semiconductor-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs).

13. The switch circuit of claim 12, wherein the SOI MOSFETs are fabricated on a silicon-on-sapphire substrate.

14. A method of controlling charge injection in a switch circuit, wherein the switch circuit comprises a plurality of switching transistors coupled in series to selectively convey a signal from an input of the series coupled transistors to an output of the series coupled transistors, comprising the steps of:

a) generating injected charge at resistively-isolated nodes between the series coupled switching transistors; and

b) conveying the injected charge to at least one node of the switch circuit that is not resistively-isolated.

15. The method of claim 14, wherein each switching transistor has an associated and corresponding charge injection control element, and wherein a drain node of each switching transistor is coupled to a first node of its associated and corresponding charge injection control element, and wherein a source node of each switching transistor is coupled to a second node of its associated and corresponding charge injection control element, and wherein each charge injection control element conveys the injected charge between the drain node and the source node of its associated and corresponding switching transistor.

16. The method of claim 14, wherein each of the switching transistors comprises an accumulated charge control (ACC) transistor.

17. The method of claim 16, wherein the ACC transistor includes an accumulated charge sink (ACS) electrically coupled to convey accumulated charge from the ACS to a gate terminal of the ACC transistor when the ACC transistor operates in an accumulated charge regime.

18. The method of claim 17, wherein a diode selectively conveys accumulated charge from the ACS to the gate terminal of the ACC transistor when the ACC transistor operates in an accumulated charge regime.

19. The method of claim 15, wherein each charge injection control element comprises a charge injection control resistor.

20. The method of claim 15, wherein the charge injection control elements comprise switching circuits having an ON-state and an OFF-state, and wherein the method further comprises a step of switching the charge control elements from the ON-state to the OFF-state at a time subsequent to a time at which each switching transistor is switched from an ON-state to an OFF-state.

21. The method of claim 20, wherein the charge injection control elements comprise charge injection control transistors.

22. The method of claim 14, wherein the switch circuit comprises a radio frequency (RF) switch.

23. The method of claim 16, wherein the ACC transistor uses a pulse method for controlling accumulated charge.

24. A switch circuit, comprising a plurality of switching transistors connected in a series configuration to selectively convey a signal from an input of the series coupled transistors to an output of the series coupled transistors, comprising:

a) means for generating injected charge at resistively-isolated nodes between the switching transistors; and

b) means, operatively coupled to the generating means, for conveying the injected charge to at least one node of the switch circuit that is not resistively-isolated.

25. The switch circuit of claim 24, wherein the conveying means comprises a plurality of charge injection control elements, and wherein each switching transistor has an associated and corresponding charge injection control element, and wherein a drain node of each switching transistor is coupled to a first node of its associated and corresponding charge injection control element, and wherein a source node of each switching transistor is coupled to a second node of its associated and corresponding charge injection control element, and wherein each charge injection control element conveys the injected charge between the drain node and the source node of its associated and corresponding switching transistor.

26. The switch circuit of claim 24, wherein each of the switching transistors comprises an accumulated charge control (ACC) transistor.

27. The switch circuit of claim 25, wherein each charge injection control element comprises a charge injection control resistor.

28. The switch circuit of claim 27, further comprising a plurality of gate resistors each having a resistance Rg, wherein a gate of each switching transistor is connected to an associated and corresponding one of the plurality of gate resistors, and wherein the plurality of gate resistors is connected to a control line that conveys a control signal to the gate of each switching transistor, and wherein a resistance Rc of each charge injection control resistor is selected according to a formula 10×

Rg/N>

Rc>

Rg/10N, and wherein N comprises a number of switching transistors in the plurality of switching transistors.

29. The switch circuit of claim 25, wherein the charge injection control elements comprise switching circuits having an ON-state and an OFF-state, and wherein a control signal selectively switches the charge injection control elements from the ON-state to the OFF-state, further comprising a means for switching the charge injection control elements from the ON-state to the OFF-state at a time subsequent to a time at which each switching transistor is switched from an ON-state to an OFF-state.

30. The switch circuit of claim 29, wherein the charge injection control elements comprise charge injection control transistors.