Power control scheme for a power amplifier

• US 20080076378A1
• Filed: 12/27/2006
• Published: 03/27/2008
• Est. Priority Date: 09/22/2006
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Lim, Lysander, Khoury, John, Leung, Vincent, Pehlke, David
• Granted Patent: US 7,974,596 B2
• Time in Patent Office: Days
• US Class Current: 455/343.1
• CPC Class Codes: H04W 52/52 using AGC [Automatic Gain Control] circuits or amplifiers

Abstract

In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.

Claims

1. A method comprising:

receiving a detected power level of a power amplifier during a current burst of a radio communication from a mobile station; and

controlling a power level of the power amplifier during a next burst of the radio communication based on the detected power level of the current burst.

2. The method of claim 1, further comprising maintaining the power level of the power amplifier for the current burst during the current burst.

3. The method of claim 1, further comprising determining a correction value for a variable gain amplifier of a transceiver based on the detected power level.

4. The method of claim 3, further comprising determining a control value for the variable gain amplifier based on the correction value, a previous correction value, a threshold level for the detected power level, and a correction value limit.

5. The method of claim 4, further comprising determining the correction value based on a sum of:

a function of a difference between the detected power level and the threshold level; and

a previous correction value.

6. The method of claim 4, further comprising receiving the threshold level and the correction value limit from a baseband processor coupled to the transceiver.

7. The method of claim 1, further comprising detecting the power level during transmission of a training sequence of the current burst.

8. The method of claim 7, wherein the training sequence is present in a midamble portion of the burst.

9. A transceiver comprising:

an interface to receive transmit power control information from a processor;

a memory to store first parameter information for a first burst of a data transmission from the transceiver; and

a controller coupled to the interface and the memory to receive the transmit power control information and the first parameter information and to determine second parameter information for a second burst of the data transmission based on the first parameter information and the transmit power control information, the second burst following the first burst.

10. The transceiver of claim 9, wherein the controller is to receive power sample information from a power amplifier (PA) coupled to the transceiver and determine the second parameter information further based on the received power sample information.

11. The transceiver of claim 10, wherein the controller is to sample the power sample information from the power amplifier during a midamble portion of the first burst.

12. The transceiver of claim 10, wherein the transceiver is to operate in a closed-loop mode if the power sample information is present, otherwise the transceiver to operate in an open-loop mode.

13. The transceiver of claim 9, further comprising a digital variable gain amplifier (DVGA) to be controlled by the second parameter information during the second burst.

14. The transceiver of claim 13, wherein the transmit power control information comprises a threshold level for the power amplifier and a maximum correction value.

15. The transceiver of claim 14, wherein the first parameter information comprises a correction value indicative of an amount of control change for the DVGA and a difference between the power sample information and the threshold level.

16. The transceiver of claim 15, wherein the controller is to determine the second parameter information according to a first algorithm if the correction value is less than a threshold, otherwise according to a second algorithm.

17. An article comprising a machine-readable medium including instructions that enable a system to:

receive a detected power level of a first burst of a multi-slot burst communication from a power amplifier (PA);

determine a power level update for a second burst of the multi-slot burst communication based at least in part on the detected power level of the first burst; and

provide the second burst to the PA responsive to the power level update.

18. The article of claim 17, wherein the instructions further enable the system to receive transmit power control information from a processor, the transmit power control information including a nominal power level.

19. The article of claim 18, wherein the instructions further enable the system to compare the transmit power control information to the detected power level and determine the power level update based at least in part on the comparison.

20. The article of claim 18, wherein the instructions further enable the system to limit the power level update to a predetermined maximum, wherein the predetermined maximum is received from the processor.

21. The article of claim 17, wherein the instructions further enable the system to control a digital variable gain amplifier (DVGA) to generate the second burst based on the power level update.

22. The article of claim 17, wherein the instructions further enable the system to sample the detected power level during a training sequence within the first burst.

23. A system comprising:

a transceiver having an interface to receive power control information from a processor, and a controller coupled to the interface to determine a power control update for a succeeding burst of a multi-slot burst communication based on the power control information and feedback information from a preceding burst of the multi-slot burst communication, the controller to determine the power control update during the preceding burst and to apply the power control update during an inter-burst period between the preceding burst and the succeeding burst;

a power amplifier coupled to the transceiver to provide the feedback information; and

an antenna coupled to the power amplifier to transmit the multi-slot burst communication.

24. The system of claim 23, wherein the transceiver is to receive the power control information from the processor in a digital form.

25. The system of claim 23, wherein the transceiver further comprises a controllable amplifier to be controlled via the power control update during the succeeding burst.

26. The system of claim 25, wherein the controllable amplifier is to be controlled by a first power control update during the preceding burst, wherein the controller is to determine the power control update using the first power control update.