Multithreaded state machine in non-volatile memory devices

• US 20080077727A1
• Filed: 09/25/2006
• Published: 03/27/2008
• Est. Priority Date: 09/25/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Yang, Yiming, Price, Mark, Woo, Nicholas, Baca, Jim S.
• Application Number:
  US11/526,360
• Publication Number:
  US 20080077727A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 2209/484 Precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

Various embodiments allow a non-volatile memory device to manage multiple process requests from an associated computing device. In at least some embodiments, a multi-threaded state machine is included in the supporting logic of the non-volatile memory device. Multiple process requests are received by the non-volatile memory device and serviced in a multi-threaded fashion.

Claims

1. A system comprising:

a non-volatile memory device having a non-volatile memory array; and

a multi-threaded state machine located on the non-volatile memory device and operably coupled with the non-volatile memory array, wherein the multi-threaded state machine is fabricated on, the same substrate as the non-volatile memory array.

2. The system of claim 1, further comprising a computing device embodying said non-volatile memory device.

3. The system of claim 2, wherein said non-volatile memory device is configured to multi-threadedly manage a plurality of process requests received from said computing device by simultaneously performing multiple operations associated with the plurality of process requests on the non-volatile memory device.

4. The system of claim 2, further comprising a command queue located on said non-volatile memory device and configured to store process requests received from said computing device.

5. The system of claim 2, wherein said non-volatile memory device is removeably attached to said computing device.

6. The system of claim 1, wherein said non-volatile memory device comprises a flash memory device.

7. The system of claim 6, wherein said flash memory device comprises a “

Not-Or”

(NOR) or “

Not-And”

(NAND) flash device.

8. A computing device comprising:

at least one antenna; and

a non-volatile memory device associated with the at least one antenna, wherein the non-volatile memory device is configured to multi-threadedly manage a plurality of process requests from the computing device by simultaneously performing multiple operations associated with the plurality of process requests on the non-volatile memory device.

9. The system of claim 8, wherein the non-volatile memory device comprises:

a non-volatile memory array module; and

a multi-threaded state machine operably coupled with the non-volatile memory array, wherein the multi-threaded state machine is fabricated on the same substrate as the non-volatile memory array module.

10. The system of claim 8, wherein said non-volatile memory device is further configured to manage said plurality of process requests by:

receiving said plurality of process requests on said non-volatile memory device; and

queuing commands associated with the plurality of process requests on said non-volatile memory device.

11. The system of claim 10, wherein said queuing comprises storing said commands in a command queue on the non-volatile memory device in an order based, at least in part, on the designated priorities of process requests associated with the commands.

12. The system of claim 8, wherein said non-volatile memory device is removeably attached to said computing device.

13. The system of claim 8, wherein said non-volatile memory device comprises a flash memory device.

14. A method comprising:

receiving a plurality of process requests on a non-volatile memory device, the process requests pertaining to operations that can be performed relative to a memory array module on the device;

queuing commands associated with the plurality of process requests on the non-volatile memory device; and

multi-threadedly performing one or more operations associated with the commands by using a multi-threaded state machine, wherein the multi-threaded state machine is fabricated on the same substrate as the memory array module and operably coupled with the memory array module.

15. The method of claim 14, wherein said non-volatile memory device is embodied on a computing device.

16. The method of claim 15, wherein said non-volatile memory device is removeably attached to said computing device.

17. The method of claim 14, wherein said non-volatile memory device comprises a flash memory device.

18. The method of claim 17, wherein said flash memory device comprises a “

Not-Or”

(NOR) or “

Not-And”

(NAND) device.

19. The method of claim 14, wherein two or more of said plurality of process requests can be received at one time.

20. The method of claim 14, wherein said queuing comprises storing said commands in a command queue on the non-volatile memory device in an order based, at least in part, on the designated priorities of the process requests associated with the commands.

21. One or more computer-readable media having computer-readable instructions thereon which, when executed by one or more processors, cause the one or more processors to implement the method of claim 14.