Hierarchical parallelism for system initialization

• US 20080077774A1
• Filed: 09/26/2006
• Published: 03/27/2008
• Est. Priority Date: 09/26/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cool, Lyle E., Zimmer, Vincent J.
• Application Number:
  US11/527,357
• Publication Number:
  US 20080077774A1
• Time in Patent Office: Days
• US Class Current: 712/212
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A technique includes using multiple processing cores of a semiconductor package to perform functions directed to booting up a computer system.

Claims

1. A method comprising:

using multiple processing cores of a semiconductor package to perform functions directed to booting up a computer system.

2. The method of claim 1, wherein the act of using comprises:

using a first processing core to perform a memory check; and

using a second processing core other than the first processing core to perform a bootup function other than performing a memory check.

3. The method of claim 2, wherein the act of using the second processing core comprises:

using the second processing core to initialize chipsets to allow memory accesses.

4. The method of claim 2, wherein the act of using the second processing core comprises:

using the second processing core to boot an operating system.

5. The method of claim 2, wherein the act of using comprises:

using the first processing core to perform the memory check in response to a communication from the second processing core.

6. The method of claim 1, wherein the act of using comprises:

using a first processing core to perform a memory check; and

using second processing cores other than the first processing core to perform a bootup function other than performing a memory check.

7. The method of claim 6, wherein the using the first processing core to perform a memory check comprises performing a memory check of a local memory to the semiconductor package.

8. An apparatus comprising:

a semiconductor package; and

multiple processing cores contained in the semiconductor package, the multiple processing cores to perform functions directed to booting up a computer system.

9. The apparatus of claim 8, wherein the semiconductor package comprises a ball grid array semiconductor package.

10. The apparatus of claim 8, wherein the multiple processing cores comprises instruction execution units.

11. The apparatus of claim 8, wherein the multiple cores comprise:

a first processing core to perform a memory check; and

a second processing core other than the first processing core to perform a bootup function other than performing a memory check.

12. The apparatus of claim 11, wherein the second processing core initializes chipsets to allow memory accesses.

13. The apparatus of claim 11, wherein the second processing core boots an operating system.

14. The apparatus of claim 8, wherein the multiple processing cores comprise:

a first processing core to perform a memory check; and

second processing cores other than the first processing core to perform a bootup function other than performing a memory check

15. The apparatus of claim 14, wherein the first processing core performs a memory check on memory local to the semiconductor package.

16. A system comprising:

a dynamic random access memory;

a semiconductor package; and

multiple processing cores housed by the package and comprising;

at least one processing core to perform a memory test of the dynamic random access memory in response to a bootup of the system; and

a processing core other than said at least one processing core to perform functions directed to booting up the system other than the memory test.

17. The system of claim 16, wherein the multiple processing cores comprises central processing unit cores.

18. The system of claim 16, wherein said processing core other than said at least one processing core initializes chipsets to allow memory accesses.

19. The system of claim 16, wherein said processing core other than said at least one processing core boots an operating system.

20. The system of claim 16, further comprising:

additional semiconductor packages, each of the additional semiconductor packages comprising multiple processing cores to perform functions directed to booting up the system.

21. An article comprising a computer accessible storage medium storing instructions that when executed cause a computer to:

use multiple processing cores of a semiconductor package to perform functions directed to booting up a computer system.

22. The article of claim 21, the storage medium storing instructions that when executed cause the computer to:

;

use a first processing core of the multiple processing cores to perform a memory check; and

use a second processing core of the multiple processing cores other than the first processing core to perform a bootup function other than performing a memory check.

23. The article of claim 22, the storage medium storing instructions that when executed cause the computer to:

use the second processing core to initialize chipsets to allow memory accesses.

24. The article of claim 22, the storage medium storing instructions that when executed cause the computer to:

use the second processing core to boot an operating system.

25. The article of claim 21, the storage medium storing instructions that when executed cause the computer to:

use a first processing core of the multiple processing cores to perform a memory check; and

use second processing cores of the multiple processing cores other than the first processing core to perform a bootup function other than performing a memory check.