System and Method for Software Debugging
First Claim
1. A debugging system, comprising:
- a processor constructed to execute a software program;
a fast-response circuit coupled to a low-level asset in the processor;
the fast response circuit configurable to extract selectively data from the low-level asset without major time-distortion of the software program executing on the processor; and
a data path constructed to transfer extracted sustained data to an evidence file.
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Accused Products
Abstract
The software debugging system provides a processor that is executing a software process, and the software process has a bug or other failure. A fast-response reporter circuit connects to a low level asset in the processor, such as a reorder buffer, commit buffer, or high speed data path. The fast response reporter circuit is configured to selectively extract data from the low-level asset, and the extracted data is transmitted to an evidence file for review and analysis. In one arrangement, a fast-response sentry circuit also connects to a low-level asset in the processor, and is configured to monitor for a predefined event. When the predefined event occurs, the fast-response sentry circuit causes an action to occur, such as activation of the reporter fast-response circuit.
62 Citations
22 Claims
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1. A debugging system, comprising:
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a processor constructed to execute a software program; a fast-response circuit coupled to a low-level asset in the processor; the fast response circuit configurable to extract selectively data from the low-level asset without major time-distortion of the software program executing on the processor; and a data path constructed to transfer extracted sustained data to an evidence file. - View Dependent Claims (4, 5, 6, 7)
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2. A debugging system, comprising:
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a processor constructed to execute a software program; a fast-response circuit coupled to a low-level asset in the processor; the fast response circuit configurable to monitor selectively sustained data from the low level asset for a predetermined event without major time-distortion of the software program executing on the processor; and wherein the fast response circuit is constructed to transmit an action signal responsive to the event.
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3. A debugging system, comprising:
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a processor constructed to execute a software program; a fast-response circuit coupled to a low-level data asset in the processor; the fast response circuit having a first portion configurable to monitor data from the low level asset for a predetermined event, and constructed to generate an action signal upon the occurrence of the predetermined event; the fast response circuit having a second portion configurable to extract selectively data from the low-level asset, and constructed to act responsive to the action signal; and a data path constructed to transmit extracted sustained data to an evidence file without major time-distortion of the software program executing on the processor. - View Dependent Claims (8, 9, 10, 11)
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12. A processor chip, comprising:
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a low-level asset; a fast-response circuit coupled to the low-level asset; the fast response circuit having a first portion configurable to monitor data from the low level asset for a predetermined event, and constructed to generate an action signal upon the occurrence of the predetermined event; the fast response circuit having a second portion configurable to extract selectively data from the low-level asset, and constructed to act responsive to the action signal; and a data path including one or more resources of the processor'"'"'s hierarchy, the data path constructed to transmit sustained evidence data to an evidence file.
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13. (canceled)
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14. A processor comprising:
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a low level asset; a fast response circuit preconfigured to monitor for an event and to extract data selectively; a high-speed data path constructed to transfer sustained data from the low level asset to the fast response circuit; wherein the processor performs the steps of; executing a central-program; detecting the event using the fast response logic; extracting data selectively using the fast response logic; and transferring the extracted data to a memory; and wherein the detecting, extracting, and transferring steps are performed without major time-distortion of the central program executing on the processor. - View Dependent Claims (15, 16)
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17. (canceled)
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18. (canceled)
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19. A debugging system, comprising:
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a processor constructed to execute a software program and having a shared high-speed data transfer bus; a fast-response circuit coupled to a low-level asset in the processor; the fast response circuit configurable to extract sustained data from the low-level asset; and a high-speed data path extending to an evidence file, the high-speed data path including the shared high-speed data transfer bus. - View Dependent Claims (20, 21, 22)
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Specification