MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS

• US 20080077937A1
• Filed: 07/27/2007
• Published: 03/27/2008
• Est. Priority Date: 07/28/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Chang-Ho, LEE, Young-Min, PARK, Jong-Wook, KIM, Mi-Jo, SHIN, Yun-Hee, KIM, Jung-Sik, SOHN, Han-Gu, LEE, Dong-Hyuk, LEE, Ho-Cheol
• Granted Patent: US 7,941,612 B2
• Time in Patent Office: Days
• US Class Current: 719/312
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Claims

1. A semiconductor memory device, comprising:

a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors;

an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors; and

an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

2. The device of claim 1, wherein the access path forming unit comprises:

a path decision unit to logically combine the external signals and generate a path decision signal;

a row and column address multiplexer for selecting one row and one column address from row and column addresses respectively applied through the ports in response to the path decision signal, and applying the address to each of a row decoder and a column decoder coupled to the shared memory area;

first and second global multiplexers for connecting a global input/output line of the shared memory area to a first data input/output line, or the global input/output line of the shared memory area to a second data input/output line, in response to the path decision signal; and

an input/output related path unit including a first input/output related circuit coupled between the first global multiplexer and a first one of the ports, and a second input/output related circuit coupled between the second global multiplexer and a second port one of the ports.

3. The device of claim 2, wherein the first input/output related circuit comprises:

a data output path circuit including an input/output sense amplifier operationally connected to the first global multiplexer, a data multiplexer operationally coupled to the input/output sense amplifier, a data output buffer connected to the data multiplexer, and a data output driver connected to the data output buffer to drive output data; and

a data input path circuit including a data input buffer in the first port, a first input driver connected to the data input buffer to primarily drive write data, and a second input driver connected to the first input driver to secondarily drive the write data.

4. The device of claim 3, wherein a plurality of memory cells disposed in a matrix of rows and columns in the shared memory area are DRAM (Dynamic Random Access Memory) cells each of which includes an access transistor and a storage capacitor.

5. The device of claim 3, wherein two input/output sense amplifiers are disposed in the shared memory area.

6. The device of claim 3, wherein the first and second global multiplexers have mutually opposed switching operations.

7. The device of claim 4, wherein the path decision unit logically combines a row address strobe signal, a write enable signal and a bank selection address individually applied through the ports, and generates the path decision signal.

8. The device of claim 4, wherein the two or more processors share, through the ports, the global input/output line of the shared memory area, a local input/output line operationally coupled to the global input/output line, a bit line operationally connected to the local input/output line by a column selection signal, a bit line sense amplifier coupled to the bit line to sense and amplify data from the bit line, and a memory cell connected to an access transistor forming a memory cell on the bit line.

9. The device of claim 1, wherein memory cells coupled to a specific word line of the shared memory area are all disabled when the interface unit is accessed by a specific address.

10. The device of claim 9, wherein the interface unit includes an internal buffer, and the semaphore area and the mailbox areas are accessed by a column address when the specific address is a row address.

11. The device of claim 10, wherein the semaphore area and the mailbox areas each have 16 bits of storage area.

12. A portable communication system, comprising:

a first processor for performing a first determined task;

a second processor for performing a second determined task; and

a random access memory including a memory cell array, first and second ports, an access path forming unit and a register unit, the memory cell array having a shared memory area accessible by both the first and second processors and first and second private memory areas accessible only by the respective first and second processors, the first and second ports each coupled to corresponding buses of the first and second processors, the access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied from the first and second processors, and the register unit having a semaphore area and mailbox areas opposedly accessible to provide an interface function for communication between the first and second processors.

13. The system of claim 12, wherein the semaphore area and mailbox areas correspond to a specific address of the shared memory area.

14. The system of claim 12, wherein:

the shared memory area may be accessed only by one of the processors that has gained control authority for the shared memory area; and

the mailbox areas may be accessed at any time by both of the processors regardless of the control authority.

15. A method for providing a host interface between processors, comprising:

coupling the processors to a multipath accessible semiconductor memory device having a shared memory area; and

performing data communication between the processors through an interface unit having a semaphore area and mailbox areas commonly accessible by the processors.

16. The method of claim 15, wherein the interface unit is mapped to a specific address in the shared memory area.

17. The method of claim 15, wherein:

the shared memory area may be accessed only by one of the processors that has gained control authority for the shared memory area; and

the mailbox areas may be accessed at any time by both of the processors regardless of the control authority.

18. The method of claim 17, wherein a first one of the processors may gain control authority for the shared memory area by:

writing data to one of the mailbox areas; and

periodically checking the semaphore area.

19. The method of claim 18, wherein a second one of the processors may write data to the semaphore area to release control of the shared memory area.

20. A semiconductor memory device, comprising:

at least one memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors; and

an interface unit having a semaphore area, mail box areas and check areas which are individually accessible in response to a specific address of the shared memory area so as to provide an interface function for communication between the processors.

21. The device of claim 20, wherein memory cells in the shared memory area are disposed in a matrix form and comprise DRAM memory cells, each cell having an access transistor and a storage capacitor.

22. The device of claim 21, wherein when the interface unit is accessed by the specific address, memory cells connected to a corresponding word line of the shared memory area are disabled.

23. The device of claim 22, wherein the interface unit is commonly enabled when the specific address is applied, and the semaphore area, the mail box areas and the check areas are accessed in response to individual column addresses.

24. The device of claim 20, wherein a mail box area and a check area are provided for each port.

25. The device of claim 24, wherein each mailbox area stores a message such as an authority request or a data/command transmission to be sent from a first processor to a second processor according to a predetermined transmission direction.

26. The device of claim 25, wherein an interrupt signal is generated to inform the second processor that the message is stored in the mail box.

27. The device of claim 26, wherein the interrupt signal is enabled when the message is written in the mail box, and disabled when the second processor has read the message stored in the mail box.

28. The device of claim 27, wherein the check area stores information indicating if the second processor has read the message stored in the mail box.

29. The device of claim 28, wherein the information stored in the check area is monitored by one or more other processors other than the second processor.

30. The device of claim 20, wherein the semaphore area and each of the mail box areas have a 16 bit storage area respectively, and the check areas respectively have a 1 or 2 bit storage area when the semiconductor memory device has two ports.

31. The device of claim 20, wherein the semaphore area has a 4 bit storage area, and the mail box areas respectively have a 32 bit storage area, and the check areas respectively have a 1 or 2 bit storage area when the semiconductor memory device has two ports.

32. The device of claim 22, further comprising a register access circuit to prevent an access to memory cells corresponding to the specific address and to enable the interface unit.

33. The device of claim 32, wherein the register access circuit comprises:

a register-address determination unit to determine if an applied address is for accessing the interface unit, and to enable the first enable signal when the address is the specific address;

a shared memory area-address determination unit to determine if a memory address for selecting any memory area among the memory areas is a memory address for selecting the shared memory area, the shared memory area-address determination unit enabling a second enable signal when the memory address is for selecting the shared memory address; and

a register access signal generation unit to generate a register access signal in response to the first enable signal and the second enable signal.

34. The device of claim 33, wherein the register access signal disables a word line drive circuit which comprises circuits for enabling a word line corresponding to the specific address, and disables a sensing/passing unit which has reading-related circuits comprising a sense amplifier for reading data in memory cells connected to the word line, and enables a data passing unit comprising writing-related circuits and input/output lines for inputting/outputting data.

35. The device of claim 34, wherein the word line drive unit comprises a sub word line driver, a normal word line enable signal generation circuit, and a word line selecting signal generation circuit.

36. The device of claim 35, wherein the register access signal prevents generation of enable signals for enabling the word line drive unit.

37. A semiconductor memory device, comprising:

at least one memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors; and

an interface unit having a semaphore area and mail box areas which are individually accessible to provide an interface function for communication between the processors, wherein the interface unit provides a first interrupt signal to a first one of the ports and a corresponding first check signal to a second one of the ports, and the interface unit provides a second interrupt signal to the second one of the ports and a corresponding second check signal to the first one of the ports.

38. The device of claim 37 wherein the check signals have the same phase as the corresponding interrupt signals.

39. The device of claim 37 wherein:

the first interrupt signal and the first check signal are enabled when a processor coupled to the second one of the ports writes a message to a mail box; and

the first interrupt signal and the first check signal are disabled when a processor coupled to the first one of the ports reads the message from the mail box.