SEMICONDUCTOR DEVICE WITH BULB-TYPE RECESSED CHANNEL AND METHOD FOR FABRICATING THE SAME

• US 20080079048A1
• Filed: 09/27/2007
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hong, Kwon, Yang, Hong-Seon, Kim, Yong-Soo, Kim, Tae-Yoon, Jang, Se-Aug, Cho, Heung-Jae, Sung, Min-Gyu, Lim, Kwan-Yong, Pyi, Seung-Ho, Lee, Seung-Ryong
• Granted Patent: US 7,838,364 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

providing a substrate having a bulb-type recessed region;

forming a gate insulating layer over the bulb-type recessed region and the substrate; and

forming a gate conductive layer over the gate insulating layer and filling the bulb-type recessed region, wherein the gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

2. The method of claim 1, wherein forming the gate conductive layer comprises:

forming a first gate conductive layer having a first thickness over the gate insulating layer;

performing a thermal treatment on the first gate conductive layer; and

forming a second gate conductive layer having a second thickness over the first gate conductive layer, wherein the second gate conductive layer fills the bulb-type recessed region.

3. The method of claim 2, wherein a temperature used in the thermal treatment is higher than temperatures used for forming the first and the second gate conductive layers.

4. The method of claim 2, wherein the thermal treatment is performed in a furnace.

5. The method of claim 4, wherein the temperature used in the thermal treatment ranges from approximately 600°

C. to approximately 1,200°

C.

6. The method of claim 2, wherein the thermal treatment is performed in an inert gas atmosphere or an oxidization gas atmosphere.

7. The method of claim 2, further comprising, after performing the thermal treatment, performing a cleaning process.

8. The method of claim 7, wherein performing the cleaning process comprises performing a dry cleaning process or performing a wet cleaning process.

9. The method of claim 1, wherein forming the gate conductive layer comprises:

providing a source gas on the gate insulating layer to form a first gate conductive layer having a first thickness;

temporarily stopping providing the source gas; and

providing the source gas again to form a second gate conductive layer having a second thickness over the first gate conductive layer.

10. The method of claim 9, wherein forming the first gate conductive layer is performed at substantially the same temperature and in the same furnace as forming the second gate conductive layer.

11. The method of claim 9, wherein during temporarily stopping providing the source gas, a temperature is maintained at substantially the same temperature as the temperature used in forming the first gate conductive layer.

12. The method of claim 9, wherein a doping gas and a purge gas are simultaneously supplied when the source gas is provided.

13. The method of claim 12, wherein, when providing the source gas is temporarily stopped, the supply of the doping gas is temporarily stopped and the supply of the purge gas is continued.

14. The method of claim 12, wherein the supply of the doping gas and the purge gas are continued when providing the source gas is temporarily stopped.

15. The method of claim 12, wherein the doping gas comprises phosphine (PH₃) or diborane (B₂H₆).

16. The method of claim 11, wherein the temperature during temporarily stopping providing the source gas ranges from approximately 450°

C. to approximately 650°

C.

17. The method of claim 9, wherein the first thickness is smaller than half of a width of the opening of the bulb-type recessed region.

18. A semiconductor device comprising:

a substrate;

a bulb-type recessed region formed in the substrate;

a gate insulating layer formed over the bulb-type recessed region and the substrate; and

a gate conductive layer formed over the gate insulating layer and filling in the bulb-type recessed region, wherein the gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

19. The semiconductor device of claim 18, wherein the gate conductive layer comprises:

a first gate conductive layer having a first thickness formed over the gate insulating layer; and

a second conductive layer having a second thickness formed over the first gate conductive layer and filling in the bulb-type recessed region.

20. The semiconductor device of claim 19, wherein the first thickness is smaller than half of a width of an opening of the bulb-type recessed region.

21. The semiconductor device of claim 19, wherein the first and the second conductive layers comprise a silicon layer.

22. The semiconductor device of claim 21, wherein the silicon layer is doped with impurities.

23. The semiconductor device of claim 19, wherein the first gate conductive layer comprises a silicon layer on which a thermal treatment is performed.

24. A method for fabricating a semiconductor device, the method comprising:

providing a substrate having a bulb-type recessed region;

forming a gate insulating layer over the bulb-type recessed region and the substrate;

forming a first gate conductive layer having a first thickness over the gate insulating layer;

performing a thermal treatment on the first gate conductive layer; and

forming a second gate conductive layer having a second thickness over the first gate conductive layer, wherein the second gate conductive layer fills the bulb-type recessed region,

wherein a discontinuous interface is formed between the first gate conductive layer and the second gate conductive layer.

25. A method for fabricating a semiconductor device, the method comprising:

providing a substrate having a bulb-type recessed region;

forming a gate insulating layer over the bulb-type recessed region and the substrate;

providing a source gas on the gate insulating layer to form a first gate conductive layer having a first thickness;

temporarily stopping providing the source gas; and

providing the source gas again to form a second gate conductive layer having a second thickness over the first gate conductive layer, wherein the second gate conductive layer fills the bulb-type recessed region,

wherein a discontinuous interface is formed between the first gate conductive layer and the second gate conductive layer.