Semiconductor devices and methods for fabricating the same

• US 20080079050A1
• Filed: 09/28/2006
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chih-Yang, Shen, C.Y., Tu, Kuo-Chi, Tzeng, Kuo-Chyuan, Huang, Kuo-Ching
• Granted Patent: US 8,012,836 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

Claims

1. A semiconductor device, comprising:

a substrate with a plurality of isolation structures formed therein, defining a first, a second areas over the substrate;

a transistor formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the first area is formed with pocket doping regions in the substrate adjacent to both source/drain region thereof and the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof;

a first dielectric layer formed over substrate, covering the transistor formed in the first and second areas;

a plurality of first contact plugs formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively; and

a second dielectric layer formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

2. The semiconductor device as claimed in claim 1, wherein the capacitor is a MIM capacitor.

3. The semiconductor device as claimed in claim 1, wherein the first area is a core area and the second area is a memory cell area.

4. The semiconductor device as claimed in claim 1, further comprising:

a third dielectric layer formed over the second dielectric layer, covering the capacitor; and

a bit line formed over the third dielectric layer, electrically contacting one of the first contact plugs.

5. The semiconductor device as claimed in claim 1, wherein the capacitor electrically connects the first contact plug electrically contacting the source region thereunder.

6. The semiconductor device as claimed in claim 4, wherein the bit-line contact electrically contacting the drain region thereunder.

7. A method for forming a semiconductor device, comprising:

providing a substrate with a plurality of isolation structures formed therein, defining a first and a second areas over the substrate;

forming a transistor on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the first area is formed with pocket doping regions in the substrate adjacent to both source/drain region thereof and the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof;

forming a first dielectric layer over the substrate, covering the transistor formed in the first and second areas;

forming a plurality of first contact plugs through the first dielectric layer, thereby electrically connecting a source region and a drain region of the transistor in the second area, respectively;

forming a second dielectric layer over the first dielectric layer; and

forming a capacitor in portions of the second dielectric layer in the second area, wherein the capacitor electrically connects one of the first contact plugs.

8. The method as claimed in claim 7, wherein the capacitor is a MIM capacitor.

9. The method as claimed in claim 7, wherein the first area is a core area, the second area is a memory cell area and the third area is a core area.

10. The method as claimed in claim 7, further comprising:

forming a third dielectric layer over the second dielectric layer, covering the capacitor;

forming a second contact plug through the third and second dielectric layers, electrically contacting one of the first contact plugs; and

forming a bitline over the third dielectric layer, electrically contacting the second contact plug.

11. The method as claimed in claim 7, wherein the capacitor electrically connects the first contact plug electrically contacting the source region thereunder.

12. The method as claimed in claim 10, wherein the second contact plug and the first contact plug contacted thereto forms a bitline contact electrically contacting the drain region thereunder.

13. A method for forming a semiconductor device, comprising:

providing a substrate with a plurality of isolation structures formed therein, defining a memory cell area and a core area over the substrate;

forming a gate stack over a portion of the substrate in the memory cell and core areas, respectively, wherein the gate stack comprises an overlying gate conductor and an underlying gate dielectric;

masking the core area by a first patterned resist layer, exposing the memory area;

forming a lightly-doped drain (LDD) region and a deeply-doped drain (DDD) region on portions the substrate exposed by the gate stack in the memory cell area;

removing the first patterned resist layer and masking portions of the memory cell area by a second patterned resist layer, exposing a portion of the substrate adjacent to a drain side of the gate stack in the memory cell area and both sides of the gate stack in the core area;

forming a lightly-doped drain (LDD) region and a pocket region in the substrate exposed by the gate stacks in the core area and the memory cell area;

removing the second patterned resist layer;

forming spacers on opposing sidewalls of each of the gate stack in the memory cell and core areas; and

forming a source/drain region in the substrate at opposing sides of the substrate exposed by the gate stacks and the spacers in the core and memory cell areas;

wherein the gate stack in the core area is formed with a source/drain region having a lightly-doped source/drain region adjacent thereto in the substrate on opposing sides thereof and the gate stack in the memory area is formed with a source/drain region with a lightly-doped source/drain region in the substrate adjacent thereto and further a pocket doping region adjacent to the lightly-doped source/drain region at a drain side.

14. The method as claimed in claim 13, further comprising:

forming a first dielectric layer over the substrate, covering the transistor formed in the first, second and third areas;

forming a plurality of first contact plugs through the first dielectric layer, thereby electrically connecting a source region and a drain region of the transistor in the second area, respectively;

forming a second dielectric layer over the first dielectric layer;

forming a capacitor in portions of the second dielectric layer in the second area, wherein the capacitor electrically connects one of the first contact plugs;

forming a third dielectric layer over the second dielectric layer, covering the capacitor;

forming a second contact plug through the third and second dielectric layers, electrically contacting one of the first contact plugs; and

forming a bitline over the third dielectric layer, electrically contacting the second contact plug.

15. The method as claimed in claim 13, wherein the substrate is doped with a first conductivity type.

16. The method as claimed in claim 13, wherein the LDD and DDD implantations implant dopants of a second conductivity type into the substrate, wherein the second conductivity type is different from the first conductivity type.

17. The method as claimed in claim 13, wherein the pocket implantation implants dopants of the first conductivity type at an angle to the surface of the substrate.

18. The method as claimed in claim 13, wherein the first area is an input/output (I/O) area, the second area is a memory cell area and the third area is a core area.

19. The method as claimed in claim 13, wherein the capacitor electrically connects the first contact plug electrically contacting the source region thereunder.

20. The method as claimed in claim 14, wherein the second contact plug and the first contact plug contacted thereto forms a bitline contact electrically contacting the drain region thereunder.