Semiconductor apparatus and manufacturing method

• US 20080079081A1
• Filed: 09/27/2007
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Hashimoto, Yasunori
• Granted Patent: US 7,741,676 B2
• Time in Patent Office: Days
• US Class Current: 257/363
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/435 Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor apparatus comprises a cell section including at least two transistors. A layer interval insulation coat is formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon. A source electrode metal coat is formed overlying the semiconductor substrate and insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and is electrically connected to the body diffusion layer and the source diffusion layer. A gate use connection hole is formed on the layer interval insulation coat overlying the gate contact use polysilicon. The gate use connection hole has a width larger than that of the trench. A gate electrode metal coat is formed on the gate use connection hole and the layer interval insulation coat. The polysilicon coat is formed at the same level or lower than the surface of the semiconductor substrate.

Claims

1. A semiconductor apparatus, comprising:

a cell section including at least two transistors, said cell including;

a drain layer including a semiconductor substrate,

a trench formed on the surface of the semiconductor substrate having a depth reaching the drain layer,

a gate electrode use polysilicon formed in the trench via a gate insulation coat,

a body diffusion layer formed overlying the semiconductor substrate, said body diffusion layer neighboring the trench and shallower than the trench, and

a source diffusion layer formed overlying the semiconductor substrate, said source diffusion layer neighboring the trench and the body diffusion layer and shallower than the body diffusion layer,

a gate contact section including;

a gate contact use concave section formed overlying the semiconductor substrate, said gate contact use concave section being separated from the cell section and formed in succession with the trench and having a larger width than that of the trench, and

a gate contact use polysilicon formed in the gate contact use concave section via an insulation coat and electrically connected to the gate electrode use polysilicon,

a layer interval insulation coat formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon;

a source electrode metal coat formed overlying the semiconductor substrate, said source electrode metal coat being insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and being electrically connected to the body diffusion layer and the source diffusion layer;

a gate use connection hole formed on the layer interval insulation coat overlying the gate contact use polysilicon, said gate use connection hole having a width larger than that of the trench; and

a gate electrode metal coat formed on the gate use connection hole and the layer interval insulation coat;

wherein the polysilicon coat is formed one of at the same level with and lower than the surface of the semiconductor substrate.

2. The semiconductor apparatus according to claim 1, wherein the upper surfaces of the gate electrode use polysilicon and the gate contact use polysilicon are lower than the surface of the semiconductor substrate, further comprising a silicon oxide coat formed between the gate contact use polysilicon and the layer interval insulation coat and being separated with an interval from a sidewall of the gate contact use concave section, the upper surface of said silicon oxide coat being the same level with the surface of the semiconductor substrate.

3. The semiconductor apparatus according to claim 1, further comprising:

a protection element use concave section formed on the surface of the semiconductor substrate with a larger width than that of the trench; and

a protection element having a PN diode formed from a protection element use polysilicon, said PN diode being formed in the protection element use concave section via an insulation coat,

wherein said layer interval insulation coat is also formed on the protection element use polysilicon, and the protection element use polysilicon is electrically connected between the source electrode metal coat and the gate electrode metal coat.

4. The semiconductor apparatus according to claim 3, wherein said insulation coat formed on the bottom surface of the protection element use concave section is thicker than the gate insulation coat.

5. The semiconductor apparatus according to claim 3,

wherein the upper surfaces of the gate electrode use polysilicon, the gate contact use polysilicon, and the protection element use concave section are lower than the surface of the semiconductor substrate,

wherein a silicon oxide coat is formed between the gate contact use polysilicon and the layer interval insulation coat and being separate with an interval from a sidewall of the gate contact use concave section, the upper surface of said silicon oxide coat being the same level with the surface of the semiconductor substrate, and

wherein the silicon oxide coat excluded between the protection element use polysilicon and the layer interval insulation coat.

6. The semiconductor apparatus according to claim 1, further comprising:

a resistance element use concave section formed on the surface of the semiconductor substrate with a larger width than that of the trench, and

a resistance element use polysilicon arranged in the resistance element use concave section via an insulation coat;

wherein said layer interval insulation coat is also formed overlying the resistance element use polysilicon.

7. The semiconductor apparatus according to claim 6, wherein the upper surfaces of the gate electrode use polysilicon, gate contact use polysilicon, and the resistance element use polysilicon are lower than the surface of the semiconductor substrate, further comprising a silicon oxide coat formed between the resistance element use polysilicon and the layer interval insulation coat and being separated with an interval from a sidewall of the resistance element use concave section, the upper surface of said silicon oxide coat being substantially the same level with the surface of the semiconductor substrate.

8. The semiconductor apparatus according to claim 6, wherein a resistance of the resistance element use polysilicon is determined by a length and a width of the resistance element use concave section as well as a coat thickness of the resistance element use polysilicon.

9. The semiconductor apparatus according to claim 6, wherein a resistance of the resistance element use polysilicon is determined by density of impurity introduced to the resistance element use polysilicon.

10. A method for manufacturing a semiconductor apparatus, comprising the steps of:

executing a trench formation step, said step at least including the sub step of forming a trench and a gate contact use concave section on a semiconductor substrate corresponding to a cell section and a gate contact section, respectively;

executing a polysilicon formation step, said step at least including sub steps of embedding polysilicon into the trench section and the gate contact use concave section via a gate insulation coat, and forming a gate electrode use polysilicon and a gate contact use polysilicon in the trench and gate contact use concave sections, respectively;

executing a layer interval insulation coat formation step, said step at least including the sub step of forming a layer interval insulation coat on the semiconductor substrate while overlying at least the gate electrode use polysilicon and the gate contact use polysilicon; and

executing a connection hole formation step, sad step at least including the sub step of forming a gate use connection hole at a prescribed position on the layer interval insulation coat overlying the gate contact use polysilicon with a width larger than the trench;

wherein said steps are executed in the above-listed order, and wherein the polysilicon does not remain on a layer upper than that of the semiconductor substrate.

11. The method as claimed in claim 10, wherein said polysilicon formation step further including the sub steps of:

forming a polysilicon coat entirely overlying the semiconductor substrate with a thickness smaller than a depth of each of the trench and gate contact use concave section;

forming a mask use insulation coat only in a concave section formed on the polysilicon coat corresponding to the gate contact use concave section;

applying etching back processing to the polysilicon coat while masking with the mask use insulation coat; and

removing the polysilicon coat from the surface of the semiconductor substrate for forming the gate electrode use polysilicon and the gate contact use polysilicon.

12. The method as claimed in claim 10, wherein said trench formation step further including the sub step of forming a protection element use concave section on the semiconductor substrate with a width larger than that of the trench;

wherein said polysilicon formation step further including sub steps of;

forming a non-dope polysilicon coat all over the semiconductor substrate;

partially decreasing a resistance of the non-dope polysilicon coat in the protection element use concave section;

forming the low and high resistance polysilicon by including the dope and non-dope polysilicon coats, respectively;

applying etching back processing to the low and high resistance polysilicons, and forming the gate electrode use polysilicon in the trench, the gate contact use polysilicon in the gate contact use concave section, and the protection element use polysilicon partially including a high resistance polysilicon in the protection element use concave section; and

forming a PN diode by applying ion injection to the high resistance polysilicon in the protection element use concave section by means of photo etching and ion injection; and

wherein said layer interval insulation coat formation step further including the sub step of forming a layer interval insulation coat on the protection element use polysilicon.

13. The method as claimed in claim 12, wherein said polysilicon formation step further including the sub step of forming the insulation coat on the bottom surface of the protection element use concave section thicker than the gate insulation coat before the non-dope polysilicon is formed.

14. The method as claimed in claim 13, wherein said polysilicon formation step further including the sub steps of:

injecting impurity ion into the semiconductor substrate of the bottom surface of the protection element use concave section using a mask at least covering the trench and having an opening on the protection element use concave section;

removing the mask; and

applying heat oxidation processing after removal of the mask; and

wherein, the insulation coat of the bottom surface of the protection element use concave section is substantially simultaneously formed thicker than the gate insulation coat when the gate insulation coat is formed.

15. The method as claimed in claim 12, wherein said polysilicon formation step further including the sub steps of:

forming a non-dope polysilicon coat all over the semiconductor substrate with a thickness smaller than the depth of each of the trench, the gate contact use concave section, and the protection element use concave section;

forming a mask use insulation coat only in a concave section formed on the non-dope polysilicon coat corresponding to the gate contact use concave section and the protection element use concave section;

introducing impurity into the non-dope polysilicon coat while masking with the mask use insulation coat;

causing the non-dope polysilicon coat becoming to the high resistance polysilicon to remain below the mask use insulation coat;

forming the low resistance polysilicon by decreasing the resistance of the non-dope polysilicon coat;

removing the low resistance polysilicon from the surface of the semiconductor substrate, while applying etching back to the low and high resistance polysilicon and masking with the mask use insulation coat for forming the gate electrode use polysilicon, the gate contact use polysilicon, and the protection element use polysilicon; and

forming a PN diode on the high resistance polysilicon of the protection element use polysilicon after removing at least the mask use insulation coat from the protection element use polysilicon by means of photo-etching and ion injection.

16. The method as claimed in claim 15, further comprising the sub steps of:

adjusting the upper surface of the mask use insulation coat to have the same height with the surface of the semiconductor substrate by using a silicon oxide coat as a mask use insulation coat;

applying an etching back processing;

removing only the mask use insulation coat from the protection element use polysilicon by means of the photo-etching and etching; and

causing the mask use insulation coat to remain on the gate contact use polysilicon.

17. The method as claimed in claim 16, further including the sub step of using a photo resist covering peripheries of the cell section, the gate contact section, and the protection element use concave section, and having an opening corresponding to the mask use insulation coat and surrounding on the protection element use polysilicon when the mask use insulation coat is to be removed from the protection element use polysilicon.

18. The method as claimed in claim 10, wherein said trench formation step further including the sub step of forming a resistance element use concave section on the surface of the semiconductor substrate with a width larger than that of the trench;

wherein said polysilicon formation step further including the sub step of forming a resistance element use polysilicon by embedding polysilicon into the resistance element use concave section; and

wherein said layer interval insulation coat formation step further including the sub step of forming a layer interval insulation coat overlying the resistance element use polysilicon.

19. The method as claimed in claim 18, wherein said polysilicon formation step further including the sub steps of:

forming the polysilicon coat all over the semiconductor substrate with a thickness smaller than the depth of each of the trench, the gate contact use concave section, and the resistance element use concave section;

forming a mask use insulation coat only in a contact section formed on the polysilicon coat corresponding to the gate contact use concave section and the resistance element use concave section; and

removing the polysilicon coat from the semiconductor substrate by applying an etching back processing to the polysilicon coat while masking with the mask use insulation coat when the gate electrode use polysilicon, the gate contact use polysilicon, and the resistance element use polysilicon are to be formed.

20. The method as claimed in claim 11, further comprising the sub step of removing the mask use insulation coat after applying the etching back processing while using a photo-resist as a mask use insulation coat.

21. The method as claimed in claim 11, further including the sub steps of:

adjusting the upper surface of the mask use insulation coat to have the same height with the surface of the semiconductor substrate by using a silicon oxide coat as a mask use insulation coat;

applying an etching back processing to the mask use insulation coat; and

maintaining the mask use insulation coat as is after the application of the etching back processing.

22. The method as claimed in claim 11, wherein said etching back processing includes isotopic etching.