Semiconductor Device Free of Gate Spacer Stress and Method of Manufacturing the Same

• US 20080079089A1
• Filed: 08/31/2007
• Published: 04/03/2008
• Est. Priority Date: 09/04/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sung-jung, Shin, Hong-jae, Suh, Bong-seok
• Granted Patent: US 7,655,525 B2
• Time in Patent Office: Days
• US Class Current: 257/384
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.

Claims

1. A semiconductor device comprising:

a substrate;

isolation regions formed in the substrate;

a gate pattern formed between the isolation regions on the substrate;

an L-type spacer adjacent to a sidewall of the gate pattern and having an end extended to the surface of the substrate;

source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions;

via plugs electrically connected with the source/drain silicide regions;

an interlayer dielectric layer which is adjacent to the L-type spacer and which fills space between the via plugs formed on the gate pattern and the substrate and; and

a signal transfer line formed on the interlayer dielectric layer.

2. The semiconductor device of claim 1, wherein a surface of the source/drain silicide regions is not lower than the surface of the substrate.

3. The semiconductor device of claim 2, wherein the source/drain silicide regions comprise nickel silicide.

4. The semiconductor device of claim 1, wherein the source/drain silicide regions are recessed and the source/drain silicide regions are electrically connected with the via plugs.

5. The semiconductor device of claim 4, further comprising a liner formed between the via plugs and the source/drain silicide regions.

6. The semiconductor device of claim 1, wherein the gate pattern includes

a gate-insulating layer which contacts with the surface of the substrate;

a gate electrode formed on the gate-insulating layer; and

a gate silicide region formed on the gate electrode.

7. The semiconductor device of claim 6, wherein a lower part of the gate silicide region is not higher than atop of the L-type spacer.

8. The semiconductor device of claim 7, further comprising a pad metal layer formed on the gate silicide region, wherein the via plugs are electrically connected with the gate silicide region through the pad metal layer.

9. The semiconductor device of claim 8, wherein the pad metal layer is extended to the sidewall of the gate silicide region.

10. The semiconductor device of claim 1, further comprising a pad metal layer formed on the source/drain silicide regions, wherein the via plugs are electrically connected with the source/drain silicide regions through the pad metal layer.

11. The semiconductor device of claim 10, wherein the pad metal layer is formed higher than the surface of the substrate.

12. The semiconductor device of claim 10, wherein the via plugs are recessed lower than the surface of the pad metal layer, and the via plugs are electrically connected with the pad metal layer.

13. The semiconductor device of claim 12, further comprising a liner formed between the via plugs and the pad metal layers.

14. The semiconductor device of claim 10, further comprising a metal or metal alloy layer formed between the pad metal layers and the source/drain silicide regions.

15. The semiconductor device of claim 1, wherein the L-type spacer is a multilayered structure.

16. The semiconductor device of claim 15, wherein the L-type spacer is formed of a combination of at least two selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.

17. The semiconductor device of claim 1, further comprising liners formed between the via plugs and the interlayer dielectric layer, and between the via plugs and the source/drain silicide regions.

18. The semiconductor device of claim 1, further comprising an upper interlayer dielectric layer formed between the interlayer dielectric layer and the signal transfer lines.

19. The semiconductor device of claim 1, further comprising an etch stopper formed between the L-type spacer and the interlayer dielectric layer.

20. The semiconductor device of claim 19, wherein the etch stopper is formed on the gate pattern.

21. A method of fabricating a semiconductor device, the method comprising:

forming isolation regions in a substrate;

forming a gate pattern on the substrate;

forming an L-type spacer layer which covers an upper region and sidewall of the gate pattern;

forming a gate spacer layer on the L-type spacer layer;

forming an L-type spacer on the sidewall of the gate pattern and extended to the substrate and a gate spacer by patterning the L-type spacer layer and the gate spacer layer, and simultaneously exposing a surface of the substrate between the gate spacer and the isolation regions;

forming a source/drain silicide region on the exposed substrate;

forming a sacrificial metal layer on the source/drain silicide region;

removing the gate spacer;

removing the sacrificial metal layer;

forming an interlayer dielectric layer which covers the gate pattern and the source/drain silicide region; and

forming via plugs electrically connected with the source/drain silicide region by vertically penetrating the interlayer dielectric layer.

22. The method of claim 21, wherein the source/drain silicide region is not lower than the surface of the substrate.

23. The method of claim 21, wherein the gate pattern includes

a gate-insulating layer which contacts the surface of the substrate;

a gate electrode formed on the gate-insulating layer; and

a gate silicide region formed on the gate electrode.

24. The method of claim 23, wherein a lower part of the gate silicide region is not higher than an upper region of the L-type spacer.

25. The method of claim 23, further comprising forming a gate sacrificial metal layer on the gate silicide region, and removing the gate sacrificial metal layer.

26. The method of claim 25, wherein the gate sacrificial metal layer is extended to be formed on a sidewall of the gate silicide region.

27. The method of claim 21, wherein the via plugs vertically penetrate the interlayer dielectric layer to form via holes which selectively expose a surface of the source/drain silicide region, and the method further comprises

forming a liner on a sidewall of the via holes and the surface of the source/drain silicide region;

and

filling the inside of the via holes with conductive material.

28. The method of claim 27, wherein the surface of the source/drain silicide region is recessed while the via holes are formed.

29. The method of claim 21, wherein the L-type spacer is a multi-layered structure comprising a combination of at least two selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.

30. The method of claim 21, further comprising forming an etch stopper which covers the gate pattern and the source/drain silicide region before forming the interlayer dielectric layer.

31. A method of fabricating a semiconductor device, the method comprising:

forming isolation regions in a substrate;

forming a gate pattern on the substrate;

forming an L-type spacer layer which covers an upper region and sidewall of the gate pattern;

forming a gate spacer layer on the L-type spacer layer;

forming an L-type spacer on the sidewall of the gate pattern and extended to the substrate and a gate spacer by patterning the L-type spacer layer and the gate spacer layer;

and exposing a surface of the substrate corresponding to between the gate spacer and the isolation regions;

forming a source/drain silicide region on the exposed substrate;

forming a source/drain pad metal layer on the source/drain silicide region;

removing the gate spacer;

forming an interlayer dielectric layer which covers the gate pattern and the source/drain silicide region; and

forming via plugs electrically connected with the source/drain silicide region by vertically penetrating the interlayer dielectric layer.

32. The method of claim 31, wherein the source/drain silicide region is not lower than the surface of the substrate.

33. The method of claim 31, wherein the gate pattern includes

a gate-insulating layer which contacts with the surface of the substrate;

a gate electrode formed on the gate-insulating layer; and

a gate silicide region formed on the gate electrode.

34. The method of claim 33, wherein a lower part of the gate silicide region is not higher than a top of the L-type spacer.

35. The method of claim 34, further comprising forming a gale pad metal layer on the gate silicide region.

36. The method of claim 35, wherein the gate pad metal layer is extended to be formed on the sidewall of the gate silicide region.

37. The method of claim 31, wherein the via plugs vertically penetrate the interlayer dielectric layer to form via holes which selectively expose a surface of the source/drain silicide region, and the method further comprises

forming a liner on a sidewall of the via holes and the surface of the source/drain silicide region;

and

filling the inside of the via holes with conductive material.

38. The method of claim 37, wherein the surface of the source/drain silicide region is recessed while the via holes are formed.

39. The method of claim 31, wherein the L-type spacer is a multi-layered structure comprising a combination of at least two selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.

40. The method of claim 31, further comprising forming an etch stopper which covers the gate pattern and the source/drain silicide region before forming the interlayer dielectric layer.