Electronic device including an inductor and a process of forming the same

• US 20080079115A1
• Filed: 09/29/2006
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Wang, James Jen-Ho
• Granted Patent: US 7,524,731 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2027/2814 with only part of the coil or of the winding in the printed circuit board, e.g. the remaining coil or winding sections can be made of wires or sheets
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/4845 Details of ball bonds
• CPC Class Codes: H01L 2224/48455 Details of wedge bonds
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series.

Claims

1. An electronic device comprising:

a substrate;

an interconnect level overlying the substrate, wherein the interconnect level comprises a first interconnect and a second interconnect;

a shock-absorbing layer overlying the interconnect level, wherein the shock-absorbing layer includes a first opening over the first interconnect and a second opening over the second interconnect; and

a first inductor including conductive traces and at least one looped wire, wherein;

the conductive traces include a first conductive trace and a second conductive trace;

a first via pad portion of the first conductive trace extends to the first opening of the shock-absorbing layer and is electrically connected to the first interconnect, and a primary pad portion of the first conductive trace overlies the shock-absorbing layer;

a secondary pad portion of the second conductive trace overlies the shock-absorbing layer, and a via portion of the second conductive trace extends to the second opening of the shock-absorbing layer and is electrically connected to the second interconnect;

a first looped wire of the at least one wire is attached to the primary pad portion of the first conductive trace; and

the first looped wire or a second looped wire of the at least one wire is attached to the secondary pad portion of the second conductive trace.

2. The electronic device of claim 1, wherein the shock absorbing layer comprises an organic polymer.

3. The electronic device of claim 1, wherein:

the conductive traces include third conductive traces overlying the shock-absorbing layer;

each of the third conductive traces includes a primary pad portion and a secondary pad portion; and

the at least one looped wire include third looped wires bonded between the primary pad portions and the secondary pad portions of adjacent third conductive traces, wherein the third looped wires are bonded at areas overlying the shock-absorbing layer.

4. The electronic device of claim 3, wherein for each of the third conductive traces, the primary pad portion is smaller than the secondary pad portion.

5. The electronic device of claim 4, wherein from a top view:

the primary pad portions of the third conductive traces are oriented along a substantially straight line; and

the secondary pad portions of the third conductive traces are oriented in a staggered formation.

6. The electronic device of claim 1, further comprising an insulating layer overlying the interconnect level and underlying the shock-absorbing layer, wherein:

the insulating layer includes an inorganic material; and

the insulating layer includes a third opening overlying the first interconnect and a fourth opening overlying the second interconnect.

7. The electronic device of claim 6, wherein:

the interconnect level further comprises bonding pads;

the insulating layer includes fifth openings overlying the bonding pads; and

the shock-absorbing layer includes sixth openings overlying the bonding pads.

8. The electronic device of claim 7, wherein:

the insulating layer abuts the first interconnect, the second interconnect, and the shock-absorbing layer;

the shock-absorbing layer includes polyimide and abuts the conductive traces; and

the conductive traces include an adhesion/barrier layer and a conductive layer.

9. The electronic device of claim 7, wherein the bonding pads and the conductive traces comprise gold.

10. The electronic device of claim 1, further comprising a radio-frequency shielding element adjacent to the first inductor, wherein the radio-frequency shielding element is in a form of a grid.

11. The electronic device of claim 1, wherein the first inductor is part of a toroidal-shape inductor.

12. An electronic device comprising:

a workpiece; and

a toroidal-shaped inductor overlying the workpiece, wherein;

the toroidal-shaped inductor includes linear inductor segments that are connected in series; and

the linear inductor segments include a first linear inductor segment having substantially parallel conductive traces and wires electrically connected between the substantially parallel conductive traces.

13. The electronic device of claim 12, wherein:

the workpiece includes a shock-absorbing layer; and

the substantially parallel conductive traces abut the shock-absorbing layer.

14. The electronic device of claim 13, wherein:

the shock-absorbing layer includes polyimide; and

the substantially parallel conductive traces include an adhesion/barrier layer and a conductive layer.

15. The electronic device of claim 12, further comprising a radio-frequency shielding element in a form of a grid.

16. The electronic device of claim 12, wherein the substantially parallel conductive traces comprise gold.

17. A process of forming an electronic device comprising:

forming an interconnect level overlying a die substrate, wherein the interconnect level comprises a first interconnect and a second interconnect;

forming a shock-absorbing layer overlying the interconnect level;

patterning the shock-absorbing layer to define a first opening that exposes the first interconnect and a second opening that exposes the second interconnect;

forming conductive traces, wherein;

the conductive traces include a first conductive trace and a second conductive trace;

a via portion of the first conductive trace extends to the first opening of the shock-absorbing layer and is electrically connected to the first interconnect, and a primary pad portion of the first conductive trace overlies the shock-absorbing layer; and

a secondary pad portion of the second conductive trace overlies the shock-absorbing layer, and a via portion of the second conductive trace extends to the second opening of the shock-absorbing layer and is electrically connected to the second interconnect; and

attaching at least one wire to the conductive traces to form an inductor, wherein;

a first wire of the at least one wire is attached to the primary pad portion of the first conductive trace; and

the first wire or a second wire of the at least one wire is attached to the secondary pad portion of the second conductive trace.

18. The process of claim 17, wherein forming the shock-absorbing layer comprises forming an organic polymer layer.

19. The process of claim 17, wherein:

forming the conductive traces comprises forming third conductive traces overlying the shock-absorbing layer, wherein each of the third conductive traces includes a primary pad portion and a secondary pad portion; and

attaching the at least one wire further comprises bonding third wires between the primary pad portions and the secondary pad portions of adjacent third conductive traces at areas overlying the shock-absorbing layer.

20. The process of claim 19, wherein forming the third conductive traces comprises forming the third conductive traces, wherein for each of the third conductive traces, the secondary pad portion is octagonal, and the primary pad portion has a shape other than octagonal.

21. The process of claim 17, wherein:

forming the interconnect level comprises forming bonding pads;

the process further comprises forming a passivation layer over the interconnect level and before forming the shock-absorbing layer, wherein the passivation layer includes an inorganic material;

patterning the passivation layer to define a third opening that exposes the first interconnect, a fourth opening that exposes the second interconnect, and fifth openings that expose the bonding pads;

patterning the shock-absorbing layer comprises patterning the shock-absorbing layer to define sixth openings that expose the bonding pads;

the process further comprises forming conductive pads over the bonding pads; and

the process further comprises attaching other wires between the conductive pads and a packaging substrate, wherein attaching the wires and attaching the other wires are performed during a same operating sequence.

22. The process of claim 17, wherein forming the conductive traces comprises:

forming a seed layer over the shock-absorbing layer and within the first opening and the second opening;

forming a patterned layer over the seed layer, wherein the patterned layer comprises third openings corresponding to a pattern for the conductive traces;

forming a conductive layer over the seed layer within the third openings;

removing the patterned layer to form exposed portions of the seed layer; and

removing the exposed portions of the seed layer, wherein the conductive traces include remaining portions of the seed layer and the conductive layer.

23. The process of claim 17, wherein forming the conductive traces comprises forming the conductive traces that include gold.