Metal layer structure of semiconductor device

• US 20080079161A1
• Filed: 12/28/2006
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Jong Hoon
• Granted Patent: US 7,495,340 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A metal layer structure of a semiconductor memory device is disclosed. The metal layer structure includes: a first metal layer to be connected to a contact plug; and a plurality of a second metal layers that are formed in parallel at a second spaced distance around the first metal layer, wherein a spaced distance of the second metal layers nearest the first metal layer maintains the second spaced distance which is wider than a first spaced distance of the second metal layers around the contact plug, and the spaced distance of the second metal layer next to the first metal layer maintains a third spaced distance, which is narrower than the second spaced distance, and the spaced distance between adjacent second metal layers gradually decreases to eventually be equal to the first spaced distance, for the second metal layers farthest from the first metal layer. Accordingly, an alignment margin can be ensured without requiring more area, and the contact plug can be connected to the next metal layer, even if an alignment error is produced.

Claims

1. A metal layer structure of a semiconductor memory device including:

a first metal layer to be connected to a contact plug; and

a plurality of second metal layers that are formed in parallel at a second spaced distance around the first metal layer,

wherein a spaced distance of the second metal layers nearest the first metal layer maintains the second spaced distance which is wider than a first spaced distance of the second metal layers around the contact plug, and the spaced distance of the second metal layer next to the first metal layer maintains a third spaced distance, which is narrower than the second spaced distance, and the spaced distance between adjacent second metal layers gradually decreases to eventually be equal to the first spaced distance, for the second metal layers farthest from the first metal layer.

2. A metal layer structure of a semiconductor memory device of claim 1, wherein the second metal layers have a length corresponding to 1.2 times to 2.0 times an overlapped length of the first metal layer and the contact plug around the contact plug, thereby maintaining a spaced distance from the first metal layer which is wider than the first spaced distance.

3. A metal layer structure of a semiconductor memory device of claim 1, wherein the spaced distance between adjacent second metal layers decreases gradually by 1 nm to 10 nm, for second metal layers farther from the first metal layer.

4. A metal layer structure of a semiconductor memory device of claim 1, wherein the spaced distance between the seventh second metal layer and eighth second metal layer near from the first metal layer, maintains the first spaced distance.

5. A metal layer structure of a semiconductor memory device of claim 1, wherein the first spaced distance is 100 nm, and the second spaced distance 115 nm.

6. A metal layer structure of a semiconductor memory device of claim 1, wherein the second metal layers are formed to have first and second widths on the region where the spaced distance next to the second metal layer gets wider, which is narrower than the first width.

7. A metal layer structure of a semiconductor memory device of claim 1, wherein the width of the second metal layer decreases by 1 nm to 10 nm as the second metal layers are further from the first metal layer.

8. A metal layer structure of a semiconductor memory device of claim 1, wherein the first width is 100 nm.