INTEGRATED CIRCUIT CHIPS WITH FINE-LINE METAL AND OVER-PASSIVATION METAL

• US 20080079461A1
• Filed: 09/29/2007
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Chou, Chien-Kang
• Application Number:
  US11/864,926
• Publication Number:
  US 20080079461A1
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48664 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48747 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48764 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48847 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48864 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

a first internal circuit in or over said silicon substrate, wherein said first internal circuit comprises a first NMOS transistor, wherein a ratio of a physical channel width of said first NMOS transistor to a physical channel length of said first NMOS transistor ranges from 0.1 to 10;

a second internal circuit in or over said silicon substrate, wherein said second internal circuit comprises a second NMOS transistor, wherein a ratio of a physical channel width of said second NMOS transistor to a physical channel length of said second NMOS transistor ranges from 0.1 to 10;

a dielectric structure over said silicon substrate;

a first interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said first interconnecting structure is connected to a first node of said first internal circuit;

a first pad over said silicon substrate, wherein said first pad is connected to said first node of said first internal circuit through said first interconnecting structure;

a second interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said second interconnecting structure is connected to a first node of said second internal circuit;

a second pad over said silicon substrate, wherein said second pad is connected to said second node of said second internal circuit through said second interconnecting structure;

a passivation layer over said dielectric structure, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer, and wherein a first opening in said passivation layer exposes said first pad, and a second opening in said passivation layer exposes said second pad, wherein said second opening has a width between 0.1 and 30 micrometers; and

a third interconnecting structure over said passivation layer and over said first and second pads, wherein said first node of said first internal circuit is connected to said first node of said second internal circuit through, in sequence, said first interconnecting structure, said first pad, said third interconnecting structure, said second pad and said second interconnecting structure, and wherein said third interconnecting structure comprises an adhesion/barrier layer, a seed layer on said adhesion/barrier layer, and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a thickness between 2 and 30 micrometers.

2. The integrated circuit chip of claim 1 further comprising a voltage converter in or over said silicon substrate, a fourth interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said fourth interconnecting structure is connected to said voltage converter, a third pad over said silicon substrate, wherein said third pad is connected to said voltage converter through said fourth interconnecting structure and exposed by a third opening in said passivation layer, a fifth interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said fifth interconnecting structure is connected to a second node of said first internal circuit, a fourth pad over said silicon substrate, wherein said fourth pad is connected to said second node of said first internal circuit through said fifth interconnecting structure and exposed by a fourth opening in said passivation layer, a sixth interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said sixth interconnecting structure is connected to a second node of said second internal circuit, a fifth pad over said silicon substrate, wherein said fifth pad is connected to said second node of said second internal circuit through said sixth interconnecting structure and exposed by a fifth opening in said passivation layer, and a seventh interconnecting structure over said passivation layer and over said third, fourth and fifth pads, wherein said voltage converter is connected to said second node of said first internal circuit through, in sequence, said fourth interconnecting structure, said third pad, said seventh interconnecting structure, said fourth pad and said fifth interconnecting structure, and wherein said voltage converter is connected to said second node of said second internal circuit through, in sequence, said fourth interconnecting structure, said third pad, said seventh interconnecting structure, said fifth pad and said sixth interconnecting structure.

3. The integrated circuit chip of claim 2, wherein said seventh interconnecting structure is used to deliver a power voltage output from said voltage converter.

4. The integrated circuit chip of claim 1 further comprising an ESD circuit in or over said silicon substrate, a fourth interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said fourth interconnecting structure is connected to said ESD circuit, a third pad over said silicon substrate, wherein said third pad is connected to said ESD circuit through said fourth interconnecting structure and exposed by a third opening in said passivation layer, a fifth interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said fifth interconnecting structure is connected to a second node of said first internal circuit, a fourth pad over said silicon substrate, wherein said fourth pad is connected to said second node of said first internal circuit through said fifth interconnecting structure and exposed by a fourth opening in said passivation layer, a sixth interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said sixth interconnecting structure is connected to a second node of said second internal circuit, a fifth pad over said silicon substrate, wherein said fifth pad is connected to said second node of said second internal circuit through said sixth interconnecting structure and exposed by a fifth opening in said passivation layer, and a seventh interconnecting structure over said passivation layer and over said third, fourth and fifth pads, wherein said ESD circuit is connected to said second node of said first internal circuit through, in sequence, said fourth interconnecting structure, said third pad, said seventh interconnecting structure, said fourth pad and said fifth interconnecting structure, and wherein said ESD circuit is connected to said second node of said second internal circuit through, in sequence, said fourth interconnecting structure, said third pad, said seventh interconnecting structure, said fifth pad and said sixth interconnecting structure.

5. The integrated circuit chip of claim 4, wherein said seventh interconnecting structure is used to deliver a power voltage input from an external circuit.

6. The integrated circuit chip of claim 1, wherein said nitride layer has a thickness between 0.2 and 1.5 micrometers.

7. The integrated circuit chip of claim 1, wherein said first opening has a width between 0.5 and 30 micrometers.

8. The integrated circuit chip of claim 1, wherein said first internal circuit comprises an NAND gate circuit.

9. The integrated circuit chip of claim 1, wherein said first internal circuit comprises an NOR gate circuit.

10. The integrated circuit chip of claim 1, wherein said first internal circuit comprises an inverter.

11. An integrated circuit chip comprising:

a semiconductor substrate;

a memory cell in or over said semiconductor substrate;

a sense amplifier in or over said semiconductor substrate, wherein said sense amplifier has a first node connected to said memory cell;

a buffer circuit in or over said semiconductor substrate, wherein said buffer circuit has a first node connected to a second node of said sense amplifier;

a logic circuit in or over said semiconductor substrate;

a dielectric structure over said semiconductor substrate;

a first interconnecting structure over said semiconductor substrate and in or over said dielectric structure, wherein said first interconnecting structure is connected to a second node of said buffer circuit;

a first pad over said semiconductor substrate, wherein said first pad is connected to said second node of said buffer circuit through said first interconnecting structure;

a second interconnecting structure over said semiconductor substrate and in or over said dielectric structure, wherein said second interconnecting structure is connected to said logic circuit;

a second pad over said semiconductor substrate, wherein said second pad is connected to said logic circuit through said second interconnecting structure;

a passivation layer over said dielectric structure, wherein a first opening in said passivation layer exposes said first pad, and a second opening in said passivation layer exposes said second pad; and

a third interconnecting structure over said passivation layer and over said first and second pads, wherein said buffer circuit has a second node connected to said logic circuit through, in sequence, said first interconnecting structure, said first pad, said third interconnecting structure, said second pad and said second interconnecting structure, and wherein said third interconnecting structure comprises an adhesion/barrier layer, a seed layer on said adhesion/barrier layer, and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a thickness between 2 and 30 micrometers.

12. The integrated circuit chip of claim 11, wherein said buffer circuit comprises an input buffer receiving a signal from said second node of said input buffer.

13. The integrated circuit chip of claim 11, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.5 micrometers.

14. The integrated circuit chip of claim 11, wherein said first opening has a width between 0.5 and 30 micrometers.

15. The integrated circuit chip of claim 11 further comprising a polymer layer between said third interconnecting structure and said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers.

16. The integrated circuit chip of claim 11, wherein said buffer circuit comprises an output buffer outputting a signal from said second node of said input buffer.

17. The integrated circuit chip of claim 11, wherein said logic circuit comprises an NAND gate circuit.

18. The integrated circuit chip of claim 11, wherein said logic circuit comprises an NOR gate circuit.

19. The integrated circuit chip of claim 11, wherein said logic circuit comprises an inverter.

20. The integrated circuit chip of claim 11, wherein said electroplated metal layer comprises a copper layer having a thickness between 2 and 30 micrometers.