Semiconductor memory apparatus

• US 20080079470A1
• Filed: 06/29/2007
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Hyun-Woo, Yun, Won-Joo
• Granted Patent: US 7,605,623 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.

Claims

1. A semiconductor memory apparatus, comprising:

a delay line configured to delay a reference clock;

a first delay block configured to delay a feedback clock;

a first phase comparator configured to compare the reference clock with an output of the first delay block;

a second delay block configured to delay the reference clock;

a second phase comparator configured to compare the feedback clock with an output of the second delay block;

a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators;

a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock; and

a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.

2. The semiconductor memory apparatus of claim 1, wherein the first delay block includes a delay unit which is the same as one of a plurality of delay units included in the delay line.

3. The semiconductor memory apparatus of claim 2, wherein the second delay block includes a unit delay which is the same as one of the plurality of delay units included in the delay line.

4. The semiconductor memory apparatus of claim 3, wherein the first and second delay blocks respectively includes two said delay units connected serially to each other.

5. The semiconductor memory apparatus of claim 1, further comprising a duty compensator configured to compensate a duty ratio of an output from the delay line to generate a delay locked clock having a compensated duty ratio.

6. The semiconductor memory apparatus of claim 1, further comprising a clock input buffer configured to buffer a system clock to generate the reference clock.

7. The semiconductor memory apparatus of claim 5, further comprising a clock output buffer configured to transfer an output of the duty compensator to a data output circuit.

8. The semiconductor memory apparatus of claim 1, wherein the locking detector includes:

a signal input block configured to recognize a locking state based on the comparison results from the first and second phase comparators;

a latch block configured to latch an output of the signal input block; and

a signal output block configured to output a locking state signal in response to a latched signal in the latch block.

9. A semiconductor memory apparatus, comprising:

a coarse delay line configured to delay a reference clock;

a fine delay line configured to delay an output from the coarse delay line;

a first delay block configured to delay a feedback clock;

a first phase comparator configured to compare the reference clock with an output of the first delay block;

a second delay block configured to delay the reference clock;

a second phase comparator configured to compare the feedback clock with an output of the second delay block;

a third phase comparator configured to compare the feedback clock with the reference clock;

a delay controller configured to control delay amounts of the coarse and fine delay lines based on comparison results from the first to third phase comparators;

a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock; and

a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.

10. The semiconductor memory apparatus of claim 9, wherein the first delay block includes a unit delay which is the same as one of a plurality of delay units included in the delay line.

11. The semiconductor memory apparatus of claim 10, wherein the second delay block includes a delay unit which is the same as one of said plurality of delay units included in the delay line.

12. The semiconductor memory apparatus of claim 11, wherein the first and second delay blocks respectively includes two said delay units connected serially to each other.

13. The semiconductor memory apparatus of claim 9, further comprising a duty compensator configured to compensate a duty ratio of an output from the delay line to generate a delay locked clock having a compensated duty ratio.

14. The semiconductor memory apparatus of claim 9, further comprising a clock input buffer configured to buffer a system clock to generate the reference clock.

15. The semiconductor memory apparatus of claim 13, further comprising a clock output buffer configured to transfer an output of the duty compensator to a data output circuit.

16. The semiconductor memory apparatus of claim 9, wherein the locking detector includes:

a signal input block configured to recognize a locking state based on the comparison results from the first and second phase comparators;

a latch block configured to latch an output of the signal input block; and

a signal output block configured to output a locking state signal in response to a latched signal in the latch block.

17. The semiconductor memory apparatus of claim 16, wherein the signal input block includes:

a first logic unit configured to perform a first logic operation on the comparison results from the first and third phase comparators;

a second logic unit configured to perform a second logic operation on the comparison results from the second and third phase comparators; and

a third logic unit configured to perform a third logic operation on outputs from the first and second logic units.

18. The semiconductor memory apparatus of claim 16, wherein the latch block includes:

a first latch configured to latch an output of the signal input block in response to a reset signal; and

a second latch configured to latch an output of the first latch in response to an inverse signal of the reset signal.

19. The semiconductor memory apparatus of claim 16, wherein the signal output block includes:

a latch configured to latch an output of the latch block in response to an inverse signal of reset signal; and

an inverter configured to invert an output of the latch.

20. A method for operating a semiconductor memory apparatus, comprising:

delaying a reference clock by a delay amount to generate a delay clock;

delaying a feedback clock by a first amount to generate a delayed feedback clock;

comparing the reference clock with the delayed feedback clock;

delaying the reference clock by a second amount to generate a delayed reference clock;

comparing the feedback clock with the delayed reference clock;

controlling the delay amount based on results of the comparing the reference clock with the delayed feedback clock and the comparing the feedback clock with the delayed reference clock;

delaying the delay clock by a modeled delay time to generate the feedback clock; and

controlling the controlling the delay amount based on the results.

21. The method of claim 20, wherein the delay amount is initially a delay time of a delay unit, and the first and second amounts are double the delay time of the delay unit.

22. The method of claim 21, further comprising compensating a duty ratio of the delay clock to generate a delay locked clock having a compensated duty ratio.

23. A method for operating a semiconductor memory apparatus, comprising;

delaying a reference clock by a first delay amount to generate a first delay clock;

delaying the first delay clock by a second delay amount to generate a second delay clock;

delaying a feedback clock by a first amount to generate a delayed feedback clock;

comparing the reference clock with the delayed feedback clock;

delaying the reference clock by a second amount to generate a delayed reference clock;

comparing the feedback clock with the delayed reference clock;

comparing the feedback clock with the reference clock;

controlling the first and second delay amounts based on comparison results of the comparing the reference clock with the delayed feedback clock, the comparing the feedback clock with the delayed reference clock, and the comparing the feedback clock with the reference clock; and

delaying the second delay clock by a modeled delay time to generate the feedback clock.

24. The method of claim 23, wherein the first and second delay amounts are initially one delay time of different delay units, and the first and second amounts are double the delay time of the respective delay units.

25. The method of claim 24, wherein the first delay amount is larger than the second delay amount.

26. The method of claim 23, further comprising compensating a duty ratio of the second delay clock to generate a delay locked clock having a compensated duty ratio.

27. A semiconductor memory apparatus, comprising:

a delay locked loop configured to perform a delay locking operation by comparing a reference clock with a feedback clock to thereby generate a delay locked clock; and

a locking detector configured to control the delay locking operation based on results of comparing a delay signal of the reference clock with the feedback clock and comparing the reference clock with a delay signal of the feedback clock.

28. The semiconductor memory apparatus of claim 27, wherein the delay signals of the reference clock and the feedback clock are generated by delaying the reference clock and the feedback clock by double a delay time of a delay unit used for the delay locking operation.

29. The semiconductor memory apparatus of claim 27, wherein the delay locked loop includes:

a delay line configured to delay the reference clock;

a first delay block configured to delay the feedback clock;

a first phase comparator configured to compare the reference clock with an output of the first delay block;

a second delay block configured to delay the reference clock;

a second phase comparator configured to compare the feedback clock with an output of the second delay block;

a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators; and

a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock.