Video Processing Architecture Having Reduced Memory Requirement

• US 20080079733A1
• Filed: 09/28/2006
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Benson, Richard, Wood, Nigel Henry, Kroon, Peter
• Granted Patent: US 8,487,947 B2
• Time in Patent Office: Days
• US Class Current: 345/502
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

In a system comprising a plurality of processors and a memory shared by at least a subset of the processors, a method for processing video data includes the steps of: (a) a first one of the processors receiving a first video frame and storing the first video frame in the memory; (b) the first one of the processors receiving at least a second video frame, receipt of the second video frame initiating a release of the first video frame from the memory; (c) the first one of the processors sending the first and second video frames to a second one of the processors together for processing by the second one of the processors; (d) the second one of the processors generating an output video frame based at least on the first and second video frames; (e) storing the output video frame in the memory by overwriting an available memory location therein, the output video frame becoming a new first video frame; and (f) repeating steps (b) through (e) until all video frames to be processed have been received.

Claims

1. In a system comprising a plurality of processors and a memory shared by at least a subset of the processors, a method for processing video data, the method comprising the steps of:

(a) a first one of the processors receiving a first video frame and storing the first video frame in the memory;

(b) the first one of the processors receiving at least a second video frame, receipt of the second video frame initiating a release of the first video frame from the memory;

(c) the first one of the processors sending the first and second video frames to a second one of the processors together for processing by the second one of the processors;

(d) the second one of the processors generating an output video frame based at least on the first and second video frames;

(e) storing the output video frame in the memory by overwriting an available memory location therein, the output video frame becoming a new first video frame; and

(f) repeating steps (b) through (e) until all video frames to be processed have been received.

2. The method of claim 1, further comprising the steps of:

determining which of the plurality of processors is available to receive the first and at least second video frames for subsequent processing; and

sending the first and at least second video frames to the available processor for processing in accordance with steps (a) through (f).

3. The method of claim 2, wherein upon storing the output video frame in the memory, the available processor is operative to indicate that it is available to receive a subsequent plurality of video frames.

4. The method of claim 2, wherein upon receiving the first and at least second video frames, the available video processor is operative to indicate that it is unavailable to receive further video frames for processing.

5. The method of claim 1, wherein the first one of the processors comprises a network processor.

6. The method of claim 1, wherein the second one of the processors comprises at least one of a video processor and a digital signal processor.

7. The method of claim 1, wherein the at least one of the video frames is received from a data network.

8. The method of claim 1, wherein the first video frame temporally precedes the second video frame.

9. The method of claim 1, wherein the available memory location is a memory location that previously stored the first video frame that has been released.

10. The method of claim 1, further comprising the step of at least one of the first and second one of the processors sending the output video frame to a destination device.

11. The method of claim 1, further comprising the step of:

during at least a portion of time that the second one of the processors is processing the first and at least second video frames, the first one of the processors sending a subsequent plurality of video frames to a third one of the processors for processing.

12. The method of claim 1, further comprising the steps of:

the second one of the processors transcoding the output video frame; and

sending the transcoded output video frame to the first one of the processors.

13. The method of claim 12, wherein the step of transcoding comprises at least one of:

encoding the output video frame in a format that is different than a format of the first and second video frames;

encoding the output video frame such that a number of frames per second of an output video stream is different than a number of frames per second of an input video stream comprising the first and second video frames; and

encoding the output video frame to have a frame size that is different than a frame size of the first and second video frames.

14. The method of claim 1, further comprising the step of sending an indicator to the first one of the processors indicating that the second one of the processors has completed processing the first and at least second video frames.

15. The method of claim 1, further comprising the steps of:

when a new second video frame is received by the first one of the processors before receiving the new first video frame from the second one of the processors, storing the new second video frame in the memory; and

the first one of the processors receiving the new first video frame from the second one of the processors, a receipt of the new first video frame initiating a release of the new second video frame from the memory if the new second video frame arrived before receiving the new first video frame.

16. In a system comprising a plurality of processors and a memory shared by at least a subset of the processors, a method for processing video data, the method comprising the steps of:

(a) a first one of the processors receiving a first video frame and storing the first video frame in the memory;

(b) the first one of the processors receiving at least a second video frame, receipt of the second video frame initiating a release of the first video frame from the memory;

(c) sending the first and second video frames to a second one of the processors together for processing by the second one of the processors;

(d) the second one of the processors generating an output video frame based at least on the first and at least second video frames, the output video frame becoming a new first video frame;

(e) when a new second video frame is received by the first one of the processors before receiving the new first video frame from the second one of the processors, storing the new second video frame in the memory;

(f) the first one of the processors receiving the new first video frame from the second one of the processors, a receipt of the new first video frame initiating a release of the new second video frame from the memory if the new second video frame arrived before receiving the new first video frame;

(g) storing the new first video frame in the memory by overwriting an available memory location therein; and

(h) repeating steps (c) through (g) until all video frames to be processed have been received.

17. The method of claim 16, further comprising the step of at least one of the first and second one of the processors sending the output video frame to a destination device.

18. A system for processing framed-based video data, the system comprising:

a plurality of processors; and

a memory shared by at least a subset of the processors;

wherein;

a first one of the processors is operative;

(i) to receive a first video frame and to store the first video frame in the memory;

(ii) to receive at least a second video frame, receipt of the second video frame initiating a release of the first video frame from the memory; and

(iii) to send the first and at least second video frames to a second one of the processors together for processing by the second one of the processors;

the second one of the processors is operative;

(iv) to generate an output video frame based at least on the first and at least second video frames, the output video frame becoming a new first video frame; and

(v) to send the output video frame to the first one of the processors for storage in the memory by overwriting an available memory location therein, the output video frame becoming a new first video frame; and

steps (i) through (v) are repeated until all video frames to be processed have been received.

19. The system of claim 18, further comprising interface circuitry coupled between the first one of the processors and a second subset of the processors, the first one of the processors and the second subset of the processors being mutually exclusive relative to one another, the interface circuitry being operative to control a flow of data between the first one of the processors and the second subset of the processors.

20. The system of claim 18, wherein the first one of the processors comprises a network processor.

21. The system of claim 18, wherein the second one of the processors comprises at least one of a video processor and a digital signal processor.

22. The system of claim 18, wherein the first one of the processors is further operative:

when a new second video frame is received by the first one of the processors before receiving the new first video frame from the second one of the processors, to store the new second video frame in the memory; and

to receive the new first video frame from the second one of the processors, a receipt of the new first video frame initiating a release of the new second video frame from the memory if the new second video frame arrived before receiving the new first video frame.

23. An apparatus for use in a frame-based video processing system, the apparatus comprising:

a memory adapted to be shared by at least a subset of video processors included in the video processing system; and

at least one network processor coupled to the memory, the network processor being operative;

(i) to receive a first video frame and to store the first video frame in the memory;

(ii) to receive at least a second video frame, receipt of the second video frame initiating a release of the first video frame from the memory;

(iii) to send the first and second video frames to given one of the video processors together for processing by the given video processor;

(iv) to receive from the given video processor an output video frame generated by the given video processor;

(v) to store the output video frame in the memory by overwriting an available memory location therein, the output video frame becoming a new first video frame; and

(vi) to repeat steps (ii) through (v) until all video frames to be processed have been received.

24. An apparatus for use in a frame-based video processing system, the apparatus comprising:

at least one video processor adapted for connection to a network processor included in the video processing system, the at least one video processor being operative;

(i) to receive from the network processor a first video frame and at least a second video frame, the first video frame being stored in a memory coupled to the network processor, the memory being shared by a subset of video processors in the video processing system, where upon receipt of the at least second video frame, the network processor initiates a release of the first video frame from the memory;

(ii) to generate an output video frame based at least on the first and second video frames;

(iii) to send the output video frame to the network processor, the output video frame being stored in the memory by overwriting an available memory location therein, the output video frame becoming a new first video frame; and

(iv) to repeat steps (i) through (iii) until all video frames to be processed have been received.