Liquid crystal display panel

• US 20080079859A1
• Filed: 09/26/2007
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Epson Imaging Devices Corporation (Seiko Group)
• Inventors: Ota, Akio
• Granted Patent: US 7,619,696 B2
• Time in Patent Office: Days
• US Class Current: 349/40
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures

Abstract

In an active matrix type liquid crystal display panel 10A of the invention, an inner shorting line 20 that is thicker than the scan lines 11 and picture lines 12 is disposed so as to surround the periphery of a display area included in the liquid crystal display panel 10A; the scan lines 11 are each connected to first electrostatic prevention circuits 15₁ and bundled by a first shorting wire 16₁; the first shorting wire 16₁ is connected to the inner shorting line 20 via at least one among second electrostatic prevention circuits 18₁; a common potential line 17 that is thicker than the inner shorting line 20 is disposed around the outer periphery of the inner shorting line 20; and at least one connection 21 is provided between the inner shorting line 20 and common potential line 17, electrically connecting each to the other. Thanks to such structure, an active matrix type liquid crystal display panel equipped with protective circuits against electrostatic damage is provided, wherein power consumption is low, there is little occurrence of flicker, and the display quality is good.

Claims

1. A liquid crystal display panel comprising:

an array substrate in which pixels are constituted by disposing a pixel electrode and a thin film transistor in each area enclosed by scan lines and picture lines arrayed as a matrix, and

a color filter substrate equipped with a common electrode;

an inner shorting line that is thicker than the scan lines and picture lines being disposed so as to surround the periphery of a display area included in the liquid crystal display panel,

the scan lines being each connected to first electrostatic prevention circuits and bundled by a first shorting wire,

the first shorting wire being connected to the inner shorting line via at least one among second electrostatic prevention circuits,

a common potential line that is thicker than the inner shorting line being disposed around the outer periphery of the inner shorting line, and

at least one connection being provided between the inner shorting line and common potential line, electrically connecting each to the other.

2. The liquid crystal display panel according to claim 1, wherein the picture lines are each connected to third electrostatic prevention circuits and bundled by a second shorting wire, the second shorting wire being connected to the inner shorting line via fourth electrostatic prevention circuits.

3. The liquid crystal display panel according to claim 1, wherein the first and second electrostatic prevention circuits are each composed of a pair of diodes connected in parallel with the anode of each connected to the cathode of the other, or else are composed of parallel circuits in which a pair of transistors with short circuits created between the gates and sources thereof are connected in opposite orientations to each other.

4. The liquid crystal display panel according to claim 2, wherein the third and fourth electrostatic prevention circuits are each composed of a pair of diodes connected in parallel with the anode of each connected to the cathode of the other, or else are composed of parallel circuits in which a pair of transistors with short circuits created between the gates and sources thereof are connected in opposite orientations to each other.

5. A liquid crystal display panel comprising:

an array substrate in which pixels are constituted by disposing a pixel electrode and a thin film transistor in each area enclosed by scan lines and picture lines arrayed as a matrix, and

a color filter substrate equipped with a common electrode;

an inner shorting line that is thicker than the scan lines and picture lines being disposed so as to surround the periphery of a display area included in the liquid crystal display panel,

the scan lines being each connected to first electrostatic prevention circuits and bundled by a first shorting wire,

the first shorting wire being connected to the inner shorting line via at least one among second electrostatic prevention circuits,

a common potential line that is thicker than the inner shorting line being disposed around the outer periphery of the inner shorting line,

on an insulator provided over the inner shorting line at least one group of multiple contact holes parallel with the common potential line being provided,

on an insulator provided over the common potential line at least one group of multiple contact holes parallel with the inner shorting line being provided, and

the inner shorting line and common potential lines being electrically connected to each other by the contact holes and by conductive films provided over the insulators.

6. The liquid crystal display panel according to claim 5, wherein the contact holes take the form of slits that extend in parallel with the inner shorting line or common potential line.

7. The liquid crystal display panel according to claim 5, wherein the picture lines are each connected to third electrostatic protection circuits and are bundled by a second shorting wire, the second shorting wire being connected to the inner shorting line via fourth electrostatic prevention circuits.

8. The liquid crystal display panel according to claim 5, wherein the first and second electrostatic prevention circuits are each composed of a pair of diodes connected in parallel with the anode of each connected to the cathode of the other, or else are composed of parallel circuits in which a pair of transistors with short circuits created between the gates and sources thereof are connected in opposite orientations to each other.

9. The liquid crystal display panel according to claim 7, wherein the third and fourth electrostatic prevention circuits are each composed of a pair of diodes connected in parallel with the anode of each connected to the cathode of the other, or else are composed of parallel circuits in which a pair of transistors with short circuits created between the gates and sources thereof are connected in opposite orientations to each other.